Abstract: A multicast processor minimizes the software resource needed to process multicast protocol and broadcast protocol for bridges and routers in a network processor based environment. The multicast forwarding processor receives multicast and broadcast Layer 2/Layer 3/Layer 4 (L2/L3/L4) frames from a network processor. During reception, a frame layer flag, a unicast/multicast flag, and a frame position flag are set. A multitask forwarding table is accessed, and the frame, unicast/multicast, and frame position flags are stored and updated. The frame, unicast/multicast, and frame position flags are then sent to a frame forwarding processor. The L2/L3/L4 frames are routed to an L2 learning processor. The L2/L3/L4 frames are received from the frame forwarding processor, and the L2/L3/L4 frames are sent to an L3/L4 processor for frame header modification. The modified L2/L3/L4 frames are received from said L3/L4 processor, and the modified L2/L3/L4 frames are sent to an L2 filter processor.

Abstract: A multi-master computer system having overlapped read and write signal with scalable address pipelining programmable increases the depth of address pipelining independently on two overlapped read and write data busses up to “N” deep requests. The system includes a local bus having an address bus, a read bus, and a write bus. Master devices are coupled to separate address, read data and write data buses. Slave devices are attached to the data busses through shared, but decoupled address, read and write data buses. An arbiter is coupled to the data bus and allows masters to compete for bus ownership. The arbiter includes read and write pipeline logic for processing and priortizing master and slave read and write data transfers across the data bus.