Abstract: The present invention is a hybrid sealing technique. According to one or more embodiments of the present invention, an unsealed lamp body is heated and a partial pinch seal is performed on a first side of the lamp body at an outer junction area. Then, a shrink seal is applied which completes the sealing process at the first side of the lamp body by sealing an inner junction area on the same side of the lamp body. The present invention retains the benefits of the shrink seal, but alleviates the difficulty associated with holding the electrode assemblies in place when performing a traditional shrink seal. In addition, the machine which holds the electrode assemblies in place is greatly simplified.

Abstract: The present invention provides a method and apparatus for accessing and using services and applications from a number of sources into a customized application. The present invention accomplishes this through an entity referred to as a web service. The web services architecture maintains a directory of services available to provide processing or services, along with the location of the services and the input/output schemas required by the services. When a request for data or services is received, appropriate services are invoked by a web services engine using service drivers associated with each service. A web services application is then generated from a runtime model and is invoked to satisfy the request, by communicating as necessary with services in proper I/O formats. In one embodiment, the web services application provides responses in the form of HTML that can be used to generate pages to a browser.

Abstract: The invention provides a system for data access in a packet-switched network, including a sender/computer including an operating unit, a first memory, a permanent storage memory and a processor and a remote receiver/computer including an operating unit, a first memory, a permanent storage memory and a processor, the sender/computer and the receiver/computer communicating through the network; the sender/computer further including device for calculating digital digests on data; the receiver/computer further including a network cache memory and device for calculating digital digests on data in the network cache memory; and the receiver/computer and/or the sender/computer including device for comparison between digital digests. The invention also provides a method and apparatus for increased data access in a packet-switched network.

Abstract: The description relates to securely and autonomously synchronizing data on geographically distributed computers. Data is distributed from a central server to geographically distributed clients. In another embodiment, data is encrypted and securely transmitted over a computer network. It uses the Secure Sockets Layer protocol to secure transmitted data. The data is transmitted via the Internet. Data is distributed in real-time. Data is provided to a user as the data updates without the user making a specific request for updated data. Portions of data are made available to only authorized users. An administrator sets permissions to control which data is transmitted to a user. The transmission of data is secure in both directions. Data transmitted to a user from a central location is secure and data transmitted to a central location from a user is secure. Data is securely transmitted to a user independent of the platform on the user's machine.

Abstract: Embodiments of the present invention are directed to a method and apparatus for heat pipe cooling of an excimer lamp. In one embodiment, a heat pipe is used to dissipate heat from an excimer lamp. The heat pipe is in direct contact with at least one electrode of the excimer lamp. In one embodiment, heat is transferred through the heat pipe to a cooling point that is electrically isolated from the lamp. In one embodiment, dissipation of heat from the cooling point is done by conventional means. In one embodiment, the heat pipe is on the inside of the lamp. In another embodiment, a heat pipe is attached to the outside of an excimer lamp. In another embodiment, two heat pipes are used, one on the inside and one on the outside of an excimer lamp. In yet another embodiment, a heat pipe is used with a flat lamp.

Abstract: The present invention provides an arc path formed in a lamp body. In accordance with one or more embodiments of the present invention, the lamp body has a plurality of closely spaced, parallel vanes which form an arc path. In one embodiment, the lamp body comprises a bottom and top plate, and a front and back sealing member. The bottom plate may be a flat plate which can be made of quartz or other suitable material. The plate has a plurality of vanes machined into it out to its edges. Alternatively, the vanes may be separate and sealed onto the bottom plate. The top plate is sealed to the bottom plate. The front and back sealing members are sealed to the plates to complete the seal of the lamp body. In another embodiment, the bottom plate is a solid block of quartz or other suitable glass material, which can have the vane pattern machined onto it stopping short of the edges. The solid block is then sealed at the top and outside edges by the top plate, without the need for front and back sealing members.

Abstract: The present invention is a class of circuits named asynchronous pulse logic (APL) circuit and designing methods for such circuits. APL replaces two of the four-phase handshakes in QDI circuits with pulses, thus breaking the timing dependencies that cause performance problems in QDI circuits. Since the pulse length in APL varies so little, it can be assumed constant. This assumption frees designers from needing to consider the effects of the inputs and outputs on the pulse length, which means timing properties can be verified locally. One embodiment of the present invention is a class of circuit design called the single-track-handshake-asynchronous-pulse-logic (STAPL), which serves as a new target for the compilation of CHP (Communication Hardware Process) programs. In one embodiment, a five-stage pulse generator is used to create a 10 transition count cycle circuit. Advantages of STAPL include a simplified solution to the charge-sharing problem and less loading from p-transistors.

Abstract: The present invention is a programming language method called Pipeline Language 1 (PL1) and its associated compiler system for generating logical circuit designs. The semantics allow the implementation to add more slack than exists in the specification, aiding the design of slack-elastic systems. In PL1, the value probe and peek are the most basic operations: receiving a value is done by first using the peek, and then acknowledging it as a separate action. Another embodiment is a PL1 compiler comprised of a technology-independent front-end module and a technology-dependent back-end module. It parses the input, converts it into BDD expressions, checks determinism conditions, generates BDD expressions for assignments and sends and converts the BDD expressions to unary representation. The back-end compiler module is technology-dependent, meaning that different back-end modules generate different circuit design types (e.g. QDI and STAPL).

Abstract: An environment is emulated in a host environment. Output generated in the emulated environment is displayed in a window of the host environment. The emulated environment's output is in the form of Postscript commands that map to the entire screen. The host environment emulates the Postscript commands and maps the output to a window. Input associated with the window is retrieved by an event driver running in the host environment. Each instance of input is referred to as an event. Each event is translated into an event of the emulated environment by an event driver. A translated event is stored in shared memory for access by a window server. The event driver notifies the window server that one or more events are queued in shared memory. The window server processes the queued events by, for example, transmitting the event to an application running in the emulated environment.

Abstract: The present invention provides a method and apparatus for mobile lightning protection. In one embodiment of the present invention, a lightning interception rod is positioned above a vehicle. In one embodiment, the rod connects to four down-conductors to conduct the current supplied by the lightning towards the ground. In one embodiment, the four down-conductors are positioned in a rectangular configuration. In one embodiment, down-conductors are covered by a insulating material. In one embodiment, the insulating material is a 3 mm thick layer of polymer. In one embodiment, one or more chains are attached to the vehicle and allowed to contact the ground. In one embodiment, two chains are attached to the vehicle. One chain is positioned at the front of the vehicle and another chain is positioned at the back of the vehicle.

Abstract: Unlike prior art synchronizers and asynchronous arbiters that produce glitches in their outputs, the present invention provides a failure-free synchronizer that can sample an arbitrary and unstable inputs while maintaining zero probability of system failure. In particular, the invention addresses the synchronization failure problem and the lack of a metastable state in prior art synchronizers. Prior attempts have shown that the conditions rex and rex (where re is the control input and x is the data input) cannot be arbitrated. To overcome this, embodiments of the present invention introduce explicit signals a0 and a1 to hold the values rex and rex, respectively. One embodiment is a fast synchronizer. It has four main components—an input integrator, an inverting component, a SEL component and an output filter. Another embodiment of the present invention is a safe synchronizer that meets the strictest QDI design requirements. Other embodiments use a standard arbiter and a killable arbiter for arbitration.

Abstract: The invention provides a method of providing commands to a command memory where a graphics processor will have commands available for execution as long as there are commands available. The command memory includes a first indicator to identify the command location most recently accessed by the graphics processor. A second indicator identifies the number of commands locations available to write commands based on the most recently accessed command location. As a result of the invention, the application processor only checks the availability of space to write commands after it has written enough commands to fill the command memory. On the graphics processor side, the command memory is never empty unless the graphics processor executes and consumes instructions faster than the instructions are written. It is also possible to associate a graphics mode with each address range. In this way, mode can be indicated without specifically sending mode information with each command.

Abstract: The present invention provides an entropy coding scheme using an adaptable prefix code. The prefix code is a binary representation of the algorithm used to compress and decompress the data. There are prefix zeros that represent the number of significant binary digits that follow the first one. According to one embodiment, this scheme works on both positive and negative integers and encodes lower order integers with a smaller length of codeword. In another embodiment, the zero integer is encoded as a special case with the shortest codeword. In yet another embodiment, the present scheme is preferred by data sets that are clustered about zero, such as image data sets that have been transformed via a wavelet transform or a discrete cosine transform.

Abstract: The present invention provides a scheme for compressing the depth, or Z, components of image data. The data is grouped into a plurality of tiles. A test is performed to determine if a tile can be compressed so that its size after compression is less than its size before compression. If so, the tile is compressed. A tile table includes a flag that can be set for each tile that is compressed. In a data transfer from memory to a graphics processor, the tile table is examined to identify those tiles that are compressed and must be decompressed prior to use. In one scheme the number of primitives that are contained in a tile are determined. If the number of primitives is less than one third of the number of pixels in a tile, an assumption is made that the tile can be compressed. For example, for an 8×8 tile, if the number of primitives is equal to or less than 21, the tile is compressed.

Abstract: The present invention provides a method and apparatus for compression rate selection. One embodiment of the present invention automatically selects a compression rate for a media signal. The embodiment determines an optimal compression rate for a media signal, compresses the signal at that rate, and stores the signal for later playback. An optimal compression rate is one which stores the media signal in the least amount of storage space without unacceptably degrading the media signal. One embodiment uses information about the media signal to determine a compression rate. In one embodiment, the information is automatically generated. One embodiment automatically generates the information using meta-information (e.g., channel, genre, etc.). Another embodiment automatically generates information using natural language parsing of a media signal description. In another embodiment, the information is generated through manual entry.

Abstract: A memory processing system and method for accessing memory in a graphics processing system are disclosed in which memory accesses are reordered. A memory controller arbitrates memory access requests from a plurality of memory requesters (referred to as “masters”). Reads are grouped together and writes are grouped together to avoid mode switching. Instructions are reordered to minimize page switches. In one embodiment, reads are given priority and writes are deferred. The memory accesses come from different masters. Each master provides memory access requests into its own associated request queue. The master provides page break decisions and other optimization information in its own queue. The masters also notify the memory controller of their latency requirements. The memory controller uses the queue and page break decisions to reorder the requests from all queues for efficient page and bank access while considering latency requirements. A sort queue may be used to reorder the requests.

Abstract: A method and apparatus for creating network services. Instead of programming or hard coding an entire web service, the invention provides the ability to easily create a module/mechanism (referred to as a template) that produces code that may be utilized to create a web service. Thus, a template is formed and utilized to create a model that can generate an application or web service. Each template is comprised of a list of features, and a model (referred to as a run time model or RTM). An RTM is an XML document that declares the structure, functionality, and behavior of a web service application (referred to as a WSA). In one or more embodiments, each feature is responsible for generating XML entities to be output in a new RTM. Each feature may obtain one or more users' input that is utilized to build an XML entity in a new RTM. Further, each feature may be processed sequentially and has the ability to modify any existing XML entities that have already been created (by other features, for example).

Abstract: The invention provides a method of generating cache indexes that reduces the likelihood that adjacent addresses will map to the same cache regions. The hashing process is optimized to be sensitive to small changes in the input data so that similar sets of input data will preferably not result in the same or even similar output data. Memory accesses of the sort performed when rendering graphical images may involve numerous accesses to relatively similar memory locations Therefore, hashing of the index values that determine where the information from the memory locations will be stored while that information is in cache decreases the likelihood of similar memory locations being stored at the same cache location. Consequently, cache efficiency and performance is improved.

Abstract: The invention comprises a computer-based system for creating, editing, and displaying works such as, for example, books, screenplays, speeches, or multimedia works, that include textual components that have a presentation metric associated with them. In one or more embodiments of the invention, the presentation metric is the time that passes when the component is delivered to the intended audience. In one or more embodiments, the components of a work are referred to as “events.” The invention creates graphical representations of events that visually display the presentation metric of the events and the temporal relationships between events. Events may be subsets of other events. In one or more embodiments, a hierarchy of events is displayed upon parallel levels, each of which represents a different level in the hierarchy.

Abstract: The invention noninvasively provides information relating to memory space allocation. Memory space allocation information is maintained in a location that is known or identifiable outside of the process for which the memory space has, been allocated. A memory space allocator maintains the information in a descriptor block. The descriptor block is updated with every allocation or deallocation of memory space. In the preferred embodiment of the invention, the descriptor block exists on a page of memory having a size equal to the native page size of the machine on which it is, operating. The memory allocator allocates memory space in units referred to as buckets that exist within a memory block. The descriptor block contains an identifier that identifies the memory space allocation information stored in that descriptor block as being controlled by a particular memory space allocator. The descriptor block also contains information that indicates how many pages are used and how many pages are free.