Abstract: A bistable switching circuit contains a pair of like-polarity input transistor circuits (Q1 and Q2) arranged in a differential configuration to receive a corresponding pair of input signals. A pair of like-polarity cross-coupled transistor load circuits (Q3 and Q4) complementary to the input transistor circuits are coupled to them. A pair of resistive elements (R1 and R2) are coupled between a voltage supply (V.sub.CC) and the load transistor circuits. An output transistor (Q5) complementary to the input transistor circuit has its control electrode and one of its flow electrodes coupled across one (Q4) of the load transistor circuits. When the input signals assume values capable of causing the output transistor to turn on, no current flows in the output transistor until regeneration occurs in the load transistor circuits -- i.e., until they switch states.

Abstract: In a memory cell array of the kind including a memory cell capacitor and a memory cell transistor connected in series between a field plate line and a bit line, both the field plate line and bit line are precharged to the same potential level. The field plate line is connected to one input of a sense amplifier and the bit line is connected to the other input. The charge and discharge of the memory cell capacitor causes equal and opposite voltage changes on the field plate line and bit line. With respect to prior art the cell signal is increased by the amount of signal on the field plate line and when sensed against a reference signal which is about one-half the amount of the cell signal, the sensed signal is about twice that obtainable in the prior art.