Abstract: A complementary metal oxide semiconductor (CMOS) structure having the source and drain regions of individual transistor devices separated from the peak impurity concentrations of the respective N- and P-wells of such devices. The CMOS structure includes trenches between the individual transistor devices, and highly doped field regions are formed in the bottom of the trenches. Each N- and P-well includes a retrograde impurity concentration profile and extends beneath adjacent trenches.

Abstract: A method and apparatus for improving the operation of infrared detectors of a type generally characterized by a semiconductive substrate of a first conductivity type which includes a detection region defined or bounded by a heavily doped backside electrode and buried layer of the first conductivity type. A charge coupled device (CCD) readout structure for transfers charge in an epitaxial layer of second conductivity type which overlies the substrate, and the detector further includes a heavily doped layer of the second conductivity type positioned between the epitaxial layer and the substrate to shield the charge carriers of the substrate from the CCD voltages. Means are provided by the present invention for the injection of minority charge carriers into the epitaxial region which are subsequently transferred to output means by the CCD.

Abstract: There is described a logic element employing fixed threshold and variable threshold transistors electrically connected together in a unique manner to form a latch. The latch can be made to retain data by keeping certain internal nodes at a high or low voltage level. As such it acts as an ordinary semiconductor memory latch, whose data can be changed by externally overriding the internal voltage levels of the latch cell. The novel results of the cell described are achieved by replacing one or several of the transistors in the latch by specially constructed transistors, whose threshold voltage can be raised or lowered upon application of a relatively high voltage pulse between their gate and substrate. By application of such a high voltage pulse, the data stored in the latch can be translated into controlled threshold shifts of the variable threshold transistors, which uniquely represent the initial latch state.

Abstract: There is described a logic element employing fixed threshold and variable threshold transistors electrically connected together in a unique manner to form a latch. The latch can be made to retain data by keeping certain internal nodes at a high or low voltage level. As such it acts as an ordinary semiconductor memory latch, whose data can be changed by externally overriding the internal voltage levels of the latch cell. The novel results of the cell described are achieved by replacing one or several of the transistors in the latch by specially constructed transistors, whose threshold voltage can be raised or lowered upon application of a relatively high voltage pulse between their gate and substrate. By application of such a high voltage pulse, the data stored in the latch can be translated into controlled threshold shifts of the variable threshold transistors, which uniquely represent the initial latch state.

Abstract: Damage to the phosphorescent screen of a cathode ray tube (CRT) by an electron beam is minimized by preventing the display of a stationary image on the screen. This is accomplished by superimposing or adding to each of the normal electron beam deflecting voltages an additional triangular offset waveform, with the combined effect of the offset waveforms being to constantly move the entire electron scan pattern over an infrequently recurring path at a slow enough rate to be imperceptible to the viewer.