Patents Represented by Attorney J. Fred Telecky

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  • Row decoder with level translator
    Patent number: 5808482
    Abstract: A combined row decoder and level translator powered by an on-chip high voltage supply results in an efficient layout, area savings and elimination of the global precharge signal resulting in additional area and power savings. In addition, power from the high voltage supply is consumed only by the level translator and wordline driver of the selected decoder resulting in additional power savings.
    Type: Grant
    Filed: March 13, 1997
    Date of Patent: September 15, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Robert N. Rountree
  • Random access memory with latency arranged for operating synchronously with a micro processor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock
    Patent number: 5808958
    Abstract: A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: September 15, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Wilbur Christian Vogley, Anthony Michael Balistreri, Karl M. Guttag, Steven D. Krueger, Duy-Loan T. Le, Joseph H. Neal, Kenneth A. Poteet, Joseph P. Hartigan, Roger D. Norwood
  • Method for reducing charge loss
    Patent number: 5792682
    Abstract: A circuit is designed with a decoder circuit (10), responsive to a first input signal (81) having a first voltage range, for producing a first output signal. An output circuit (11), responsive to the first output signal, produces a second output signal (26) having a second voltage range. The second voltage range includes a voltage less than a least voltage of the first voltage range and a voltage greater than a greatest voltage of the first voltage range.
    Type: Grant
    Filed: April 23, 1997
    Date of Patent: August 11, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Hugh P. McAdams, Jeffrey Koelling
  • Apparatus and method for a direct-sense sense amplifier with a single read/write control line
    Patent number: 5790467
    Abstract: In a dynamic random access memory, the sense amplifiers associated with the storage cells have the direct sense circuitry (MNEW, MNWE.sub.--, MNRD, MNRD.sub.--) included therewith to minimize the effects of parasitic impedance. In addition, the Y-select circuits (MNYS, MNYS.sub.--) are combined with the read/write enable circuits (MNWE, MNWE.sub.--, MNRD, MNRD.sub.--) to eliminate a transistor pair, thereby reducing the required layout area. By locating the Y-select (MNYS, MNYS.sub.--) circuits between the sense amplifier MNWE, MNWE.sub.--, MNRD, MNRD.sub.--) and the local input/output lines (LIO, LIO.sub.--), the WRITE-ENABLE and the READ-ENABLE signals can be combined in a single signal.
    Type: Grant
    Filed: November 25, 1996
    Date of Patent: August 4, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Brent S. Haukness, Hugh McAdams