Abstract: A circuit employable as a differential multiplexer (10, 310, or 610) or as a differential logic gate (110, 210, 250, 410, or 510) of either the OR/NOR or EXCLUSIVE OR/EXCLUSIVE NOR type contains four pass gates that operate on four circuit input signals and are controlled by two additional circuit input signals. Two of the pass gates drive a bipolar transistor serially coupled to a first FET driven from the other two pass gates. Likewise, the second pair of pass gates drive another bipolar transistor serially coupled to another FET driven from the first pair of pass gates. The bipolar transistors supply respective circuit output signals. The two FETs are of a first polarity. The circuit preferably includes a pair of FETs of a second polarity opposite to the first polarity. The second pair of FETs are arranged so as to provide output pull-up/pull-down assistance for the bipolar transistors.

Abstract: The driver circuit comprises drive means (Q2) for drawing an output current from a bus line (13) in a first state of the circuit. An output diode (S1) in the path of the output current is reverse biased in a second state of the circuit to isolate the drive means from the bus line. A control current (I.sub.Q2B) for the drive transistor is drawn from the bus line (13), beyond the output diode (S1). By this means, power dissipation (heat) within the driver circuit due to the control current is eliminated. The driver circuit also comprises means (26, S3, P1) for biasing the output during connection of the circuit to a live bus line, so as to reduce noise for other circuits connected to the bus line.

Abstract: In a memory element comprising interconnected logic gates with field effect transistors metastable states are to be avoided. The device's immunity against staying in metastable states is considerably raised by coupling a supply terminal of each logic gate to a power supply voltage via a base-emitter path of a bipolar transistor that has its collector coupled to the logic gate's output.

Abstract: A reduced-temperature two-step silicon deposition performed at different silicon sources is used in forming a composite monosilicon/polysilicon layer (20/24/26) on a body that contains a monosilicon region (10) and an adjoining dielectric regin (12). The first step entails selectively depositing silicon, preferably using dichlorosilane as a CVD silicon source, to grow a first monosilicon layer (20) on exposed monosilicon at an average body temperature less than or equal to 950.degree. C. Substantially no silicon accumulates on exposed dielectric material during the first step. The second step entails non-selectively depositing silicon, preferably using silane as a CVD silicon source, at an average body temperature less than or equal to 950.degree. C. to grow a second monosilicon layer (24) on the first monosilicon layer and to simultaneously grow a polysilicon layer (26) on the exposed dielectric material.

Abstract: Electrical connections to specified semiconductor or electrically conductive portions (18, 26, and 30) of a structure created from a semiconductive body (10) are created by a process in which a titanium contact layer (34) is deposited on the structure over the specified portions. An electrically conductive barrier material layer (36) which consists principally of non-titanium refractory material is formed over the contact layer. The resulting structure is then annealed at a temperature above 550.degree. C. in order to lower the contact resistance. The anneal is preferably done at 600.degree. C. or more for 10-120 seconds in a gas whose principal constituent is nitrogen. An electrically conductive primary interconnect layer is formed over the barrier material layer after which all three layers are patterned to create a composite interconnect layer.

Abstract: A circuit formed with an input stage (20) and an output stage (22 or 28) uses capacitively enhanced switching to improve switching speed without significantly raising steady-state current utilization. The output stage contains a pair of amplifiers (A1and A2) that respond to complementary signals (V.sub.M1 and V.sub.M2) produced by the input stage. The amplifiers are coupled to a pair of corresponding nodes (N1 and N2). A third amplifier (A3) in the output stage has a control electrode coupled to one of the nodes, a flow electrode coupled to the other node, and another flow electrode coupled to a further node (N3). A current supply (24) provides current at the further node. A charge/discharge element (CD1) produces a capacitive-type charge/discharge action between the further node and a source of a reference voltage (V.sub.R1).

Abstract: A monolithic integrated circuit contains a field-programmable logic architecture centered on a single array of programmable gates that perform either logical NAND or logical NOR operations. Foldback loops can be readily programmed through the array to enable the user to achieve different numbers of logic levels.

Abstract: In hermetically sealing a base structure (10) of a ceramic package for a semiconductor device to a cap structure (12) of the device, one or more venting slots (36) are initially provided in the base sealing layer (16) or in the cap sealing layer (26). The base and cap structures are then fused together along the two sealing layers and electrical leads (20) by bringing the structures into contact and heating them to a temperature high enough to cause the sealing material to flow readily. The venting slots allow air to escape during the fusing step. This inhibits the formation of air bubbles along the sealing interface and thereby improves the hermeticity of the seal. The structures are subsequently cooled to harden the sealing layers into a unitary layer (28).

Abstract: An integrated circuit (10, 22) contains an active bypass (36) that inhibits high-frequency supply-voltage variations caused by interaction of the circuitry elements (28) with the parasitic inductances (L.sub.HE, L.sub.HP, L.sub.LP, and L.sub.LE) associated with the power supply lines (16.sub.H /24.sub.H /26.sub.H /32.sub.H and 16.sub.L /24.sub.L /26.sub.L /32.sub.L) for the circuit. The bypass centers around a transistor (Q.sub.BP) coupled between the supply lines. An activation circuit (38) provides the transistor with a control signal (V.sub.C) to activate the transistor. A sensing capacitor (C.sub.S) provides a capacitive action between the transistor control electrode and one of the supply lines.

Abstract: The size of a fusible link (22C.sub.F) created from part of a metal layer (22) is controlled by an oxidation performed in a deposition chamber that is also used for depositing a dielectric layer (30) over the fuse structure. The metal layer serves as a diffusion barrier between semiconductor material (14 and 16) and another metal layer (24).