Abstract: A method for controlling a high speed memory unit M to be read from, and written to, as initiated by clock signals of comparable speed, this method involving: providing a timing coordinator unit with bi-stable store for storing and presenting certain input signals to the memory unit in conjunction with the clock signals so as to be immediately useable thereby and so that the memory unit can responsively output data to a user stage; these input signals being arranged to include commands R/W to Read or Write, Address signals and Data signals; and the memory unit being maintained in “ready-to-read” condition at all times except during receipt of write commands.

Abstract: An arrangement for automatically, selectably diverting, different-weight checks being transported along a prescribed track with divert-blade means at a prescribed divert-station therealong, said checks comprising "standard" and "non-standard", heavier versions, this arrangement comprising, in combination with the foregoing:weight sense means, disposed along said track, upstream of said divert station, for sensing at least a mass characteristic of passing checks and outputting mass-indicating signals SS representative thereof; actuate means arranged to thrust said blade means across said track and associated actuate-adjust means for adjusting actuation-torque of said actuate means responsive to associated torque-adjust signals AA input thereto; and control means arranged to receive said mass-indicating signals SS, manipulating them and applying associated torque-adjust signals AA to said actuate-adjust means whereby to automatically adjust and control the torque applied to said blade means according to the sen

Abstract: Apparatus for transporting and processing documents and maintaining a preset nominal inter-document gap, g.sub.nom therebetween, this apparatus including transport stage for picking each document from an input stack and advancing it toward a destination at a controlled rate; a sensor unit for sensing the distance g between the so-moved document and the following document; and a control stage for determining the variance .gradient.g, between g.sub.nom and g, while driving each successive document along a feed path from the input stack at adjustable times; with the sensor unit inputting the control means which is adapted to responsively determine the variance-distance .gradient.g, and to thereupon control the transport stage to adjust the acceleration or deceleration of a following document and so tend to reduce this variance-distance .gradient.g.

Abstract: In a check processing array, an imaging/illumination arrangement for illuminating and imaging checks at one or several imaging sites as they are rapidly, continuously transported past two or more imaging stations, each station having, as its illumination source, a hollow Lambertian integrating vessel, housing lamps which project a highly uniform, diffuse Lambertian illumination-beam to its respective imaging site.

Abstract: Disclosed is a combined "streak-detector" and "ink-lever flow detector" on opposite sides of a single printed circuit board; each detector comprising a pair of parallel printed circuit segments adapted to be "shorted" by interposition of conductive ink and coupled to register this event in an associated detect-logic stage.

Abstract: A method for adapting a computer unit array having an internal power supply for supplying an associated external peripheral unit with DC power from this power supply; wherein the computer unit is provided with a removable "power panel" secured in a sidewall and is made to comprise a metal strip provided with electrical terminals therein adapted for coupling to the power supply, and for so powering such a peripheral unit.

Abstract: Systems allowing smooth, trouble-free, "transparent" switchover from a "Primary clock" to a "Secondary clock", with no loss of clock or essential pulse-width, and where the "Secondary clock" may be completely separate from, and independent of, the "Primary clock.

Abstract: A "bit-sliced" construction cache module dictates dual TAG RAM Structures and dual invalidation queues, yielding enhanced performance: putting half the TAG array in each of two cache arrays, and allowing each to handle only one-half of the possible address values. Preferably, one half-module handles ZERO least-significant bits and the other handles ONE least-significant bits. Processor operations and invalidation operations can be "overlapped", and even operate simultaneously.