Abstract: A test device (40) has a patterned conductive layer (42 or 44) particularly adapted for use in an E-beam probe system (FIG. 3) to study how local electric fields influence probe voltage measurements. The layer is composed of two or more conductors (A and B.sub.J C and D.sub.J) separated from each other. Each conductor has a group of fingers. The fingers (F1.sub.p, F0.sub.p, F2, F0.sub.Q and F1.sub.Q) run parallel to one another and are at least partially interdigitated. The width of each finger is constant along its length. The widths of the fingers and the spacings between them vary from finger to finger according to a selected pattern.

Abstract: A switching device (22) responsive to an input voltage V.sub.A is powered by low and high internal supply voltages V.sub.L and V.sub.H. The device changes state as V.sub.A -V.sub.L passes a threshold voltage V.sub.T. After the device makes a desired change of state in response to rising V.sub.A, a hysteresis circuit (24) temporarily decreases V.sub.T below that which would otherwise be present. Likewise, after the device makes a desired change of state in the opposite direction when V.sub.A is falling, the hysteresis circuit temporarily decreases V.sub.T. In both cases, V.sub.T later automatically returns to its original value. This dynamic hysteresis prevents spikes in V.sub.L and V.sub.H from causing undesired changes in state.

Abstract: An on-chip regulated substrate bias voltage generator for an MOS integrated circuit includes a ring oscillator (10) for developing a true signal and its complement. The signals are applied to a charge pump (12) that includes two capacitors (C1 and C2) and a plurality of rectifiers (22, 24, and 26). The charge pump produces a substrate bias voltage (V.sub.BB) which is supplied to the gate of a depletion-mode field-effect transistor (28) whose source receives a reference voltage (V.sub.SS). The transistor forms part of a control circuit (14) coupled to the ring oscillator. In the N-channel case, the charge pumping action on the substrate drives the substrate bias negative until it reaches the sum of the reference voltage and threshold voltage of the depletion-mode transistor. This enables the control circuit to control the operation of the ring oscillator so as to regulate the substrate bias voltage.

Abstract: A double-ended code converter (10) contains three or more like-configured amplifiers (T.sub.O -T.sub.M+1). Each has a first flow electrode (E1), a second flow electrode (E2), and a control electrode (CE) for receiving a signal to control charge carriers moving from the first electrode to the second. The first electrodes are coupled to a circuit supply (12) which may be a current source or a voltage supply. The second electrodes are selectively coupled to one or the other of a pair of lines (L.sub.B and L.sub.BN) which are coupled to respective load elements (14.sub.B and 14.sub.BN) to provide a pair of complementary signals (V.sub.B and V.sub.BN).

Abstract: A protection device (14) for an integrated circuit (12) created on a semiconductor body (24 and 26) utilizes one or more semiconductor diodes (D.sub.L and/or D.sub.H) that have subsurface PN junctions (46 and/or 56) for preventing high-magnitude voltages, such as those generated by electrostatic discharge, from damaging sensitive electronic elements of a protected circuit component (16) formed from part of the body. The device is fabricated by an epitaxial layer/double buried region process.

Abstract: A semiconductor PROM contains a group of PROM cells (12) each consisting of a pair of opposing diodes oriented vertically with their common intermediate region (22 and 24) fully adjoining a recessed oxide insulating region (16). The PN junction (30) of the upper diode of each pair lies in non-monocrystalline semiconductor material. A composite buried layer consisting of buried regions (32) which adjoin the insulating region below the lower cell regions (20) and a buried web (44) which laterally surrounds each buried region is employed to improve programming efficiency as well as provide intermediate electrical connections.

Abstract: A field-programmable logic architecture is centered on a single array of programmable gates that perform either logical NAND or logical NOR operations. Foldback loops can be readily programmed through the array to enable the user to achieve different numbers of logic levels.

Abstract: A semiconductor PROM containing a group of PROM cells (12) each consisting of a pair of opposing diodes oriented vertically with their common intermediate region (22) fully adjoining a recessed oxide insulating region (16) is fabricated by a process in which the insulating region serves as a mask to control the lateral extents of the dopants utilized to define the diodes. The intermediate cell regions are ion implanted to obtain maximum dopant concentration near their mid-points. This facilitates programming operation.

Abstract: During the deposition of a metallic layer on an N-type semiconductive region to form a Schottky diode in a structure placed in a highly evacuated chamber, at least one selected gas is introduced into the chamber to control the forward voltage across the diode.

Abstract: A circuit capable of simulating a transistor or a semiconductor diode with controllably adjusted voltage characteristics contains a main transistor (Q0). An input voltage (V.sub.CS) to a control system (8) is amplified with a gain set by a pair of resistors (R1 and R2) to produce a control voltage (V.sub.C) for the transistor. This downscales the forward voltage characteristics of the circuit from those of the transistor. A floating power supply (10) in series with the control electrode of the transistor permits upscaling or further downscaling of the circuit voltage range.

Abstract: A circuit switches with a hysteresis defined by separately controllable thresholds which can be made largely independent of temperature and fabrication conditions. The circuit contains a pair of differential portions (21 and 22) and an arithmetic component (24). The hysteresis is introduced into the circuit by using positive feedback to control the position of a switch (23) in such a manner as to change the transconductance of the circuit as it is switching.

Abstract: A pair of complementary logic gates (A and B) are used to test for faults in a group of electronic components (C1-C3) which provide respective component signals (S1-S3) indicative of their condition. One (A) of the gates ideally generates the logical OR or NOR of the component signals. The other (B) ideally generates their logical AND or NAND. The test procedure involves providing the components with information patterns that would ideally cause all the component signals to go to a logical "0" in one step and to logical "1" in another step. The actual values of the gate output signals (OA and OB) during these two steps are then compared with the respective ideal values to assess the condition of the components.

Abstract: An input portion (4, 6) of a differential amplifier circuit amplifies a differential input signal to produce an amplified signal between a pair of terminals. A summing section contains two complementary pairs of like-polarity amplifiers (13, 14 and 19, 20). Each has a first flow electrode, a second flow electrode, and a control electrode. A substantially constant bias voltage is supplied to the control electrodes of the first pair (13, 14) whose second electrodes are respectively coupled to the second electrodes of the second pair (19, 20). Their first electrodes are respectively coupled to the terminals and to corresponding impedance elements (11, 12). The control electrodes of the second pair are coupled together to receive a voltage dependent on the voltage at the second electrode of one (13) of the first pair so as to produce a representative output signal at the second electrode of the other (14) of the first pair.

Abstract: A NOR gate consisting of a set of input FET's (Q1.sub.1 -Q1.sub.M) has a clamp (12/ Q2) that, when at least one of the input FET's is turned on, clamps the logical low level of the gate output voltage at a value which is largely constant irrespective of how many of the input FET's are conductive.

Abstract: A portion (28) of photosensitive material is created by an underetching/shadowing technique in such a manner as to have an extremely narrow width.

Abstract: A steering circuit (10) in a differential amplifier having a pair of differentially arranged input amplifiers (A1 and A2) steers current from a pair of current sources (11 and 12) in such a way as to enhance slew rate without increasing offset voltage. The steering circuit is formed with a pair of steering amplifiers (A3 and A4) arranged in a differential configuration through a pair of resistors (R3 and R4).

Abstract: A structure having substantial surface evenness is created by a method in which an insulating layer (24) that has an upward protrusion (26) is formed on a patterned conductive layer (20) having a corresponding upward protrusion (22). A further layer (28) having a generally planar surface is formed on the insulating layer. Using an etchant that attacks the further layer much more than the insulating layer, the further layer is etched to expose at least part of the insulating protrusion. The further layer and the insulating layer (as it becomes exposed) are then etched with an etchant that attacks both of them at rates not substantially different from each other. This brings the upper surface down without exposing the conductive layer, particularly its upward protrusion.

Abstract: An absolute-value analog-to-digital converter containing a chain of matched main absolute-value differential amplifiers (A.sub.1 -A.sub.N) has a gain control for regulating the gain of each main amplifier utilizing an auxiliary absolute-value differential amplifier (A.sub.GC) matched to the main amplifiers. An offset control in the converter drives the offsets of the amplifiers toward zero by using a further absolute-value differential amplifier (A.sub.OC) matched to the other amplifiers. The gain and offset control are implemented with suitable feedback circuitry.

Abstract: In fabricating a PROM cell, an electrical isolation mechanism (44 and 32) is formed in a semiconductive body to separate islands of an upper zone (36) of first type conductivity (N) in the body. A semiconductor impurity is introduced into one of the islands to produce a region (48) of opposite type conductivity (P) that forms a PN junction laterally bounded by the island's side boundaries. A highly resistive amorphous semiconductive layer (58) which is irreversibly switchable to a low resistive state is deposited above the region in such a manner as to be electrically coupled to the region. A path of first type conductivity extending from the PN junction through another of the islands to its upper surface is created in the body to complete the basic cell.

Abstract: A voltage reference for providing a reference voltage (V.sub.AB) between a pair of terminals (A and B) contains a diode (D) and a bipolar transistor (Q) whose base is coupled to one electrode of the diode. The collector of the transistor is coupled to a node (C) between one of the terminals (A) and the other electrode of the diode. The emitter of the transistor is coupled to the other terminal (B).