Abstract: For a data processing system which employs a cache memory, the disclosure includes both a method for lowering the cache miss ratio for requested operands and an example of special purpose apparatus for practicing the method. Recent cache misses are stored in a first in, first out miss stack, and the stored addresses are searched for displacement patterns thereamong. Any detected pattern is then employed to predict a succeeding cache miss by prefetching from main memory the signal identified by the predictive address. The apparatus for performing this task is preferably hard wired for speed purposes and includes subtraction circuits for evaluating variously displaced addresses in the miss stack and comparator circuits for determining if the outputs from at least two subtraction circuits are the same, indicating a pattern which yields information which can be combined with an address in the stack to develop a predictive address.

Abstract: Binary-Coded-Decimal to binary (DTB) and binary to Binary Coded Decimal (BTD) instructions are executed by an address and execution (AX) chip, a decimal numeric (DN) chip, and a cache. For a DTB instruction, the DN chip receives the operand to be converted from the cache, saves the sign, and stores it in a conversion register. When a bit is converted, a Ready-to-Send signal is sent on a COMFROM bus with a Ready-to-Receive Command on a COMTO bus causes the AX chip to accept the bit and the DN chip to generate the next bit until the resultant operand is produced. If the operand to be converted is negative, the DN chip inverts each remaining bit after the first "1" to obtain a two's-complement result. The result in either case is sent to the cache. For a BTD instruction, the AX chip receives the operand to be converted from the cache, send the sign bit to the DN chip and then the bits of the operand when the Ready-to-Send and Ready to Ready-to-Receive signals are produced.