Abstract: A control circuit for a switching regulator comprised of silicon controlled rectifiers and inductive reactors is disclosed. The control circuit provides for fault detection and voltage regulation while using these output as control signals for a frequency variable gating mechanism to trigger the switching regulator so as to provide its maximum output capability.

Abstract: The invention disclosed reduces unrecoverable read errors from a magnetic tape resulting from the apparent lack of a cyclic check character (CCC), sometimes referred to as a cyclic redundancy check character, or a longitudinal check character (LCC), sometimes referred to as a longitudinal redundancy check character. The detector provides a variable read window to synchronize receipt of the CCC and/or LCC with their associated data blocks even though the CCC and/or LCC was not written in the appropriate time frame called for by the write specification of the tape in question.

Abstract: A positive pressure apparatus for depositing a thin, even layer of an adhering liquid material to seal openings on a metallic clad film-type carrier is disclosed. The openings, on the film side opposite the metallic lamination, are covered prior to the etching process in order to minimize undercutting by the etching material on the metallic lamination and to provide support for the resulting integrated circuit leads. The apparatus uses a positive pressure mechanism to force the fluid material through a porous ceramic element in order to obtain uniform flow.

Abstract: A memory organization system is disclosed which comprises an improved, bit-organized RAM system. The invention substantially limits errors within the RAM system such that they are error-correctible by existing error detection and correction means. Commonly available RAMs are organized on a logic board such that each bit of a word being addressed is provided by a different RAM chip and is driven by a distinct driver. In this manner a malfunction in either a chip or a driver circuit results in only a one-bit error per word and overall system performance is also improved.

Abstract: In an input/output data processing system employing local and remote memory and paged data storage, memory steering is included in the address development, thus eliminating the need for special memory configuration logic. Words used in constructing absolute memory addresses for data fetches include address portions referencing local/remote memory, specific memory, and/or lack of memory residence for effecting a system fault procedure.

Abstract: An input-output processing system which performs communication and control functions in a larger data processing system includes a processor for address development to paged memory and program instruction execution for I/O command sequences. In generating memory addresses, instructions are provided an address syllable which references a processor register as an index and a displacement. The contents of the register and the displacement define a memory effective address. A scratchpad memory is provided for storing page table words in levels corresponding to priority levels of processes, and stored page table words are accessed according to the least significant bits of the page number of the effective address. A page base address is taken from an accessed page table word and is concatenated with the effective address to define an absolute memory address.