Abstract: The invention interconnects stacks executing the same protocol in the same node by means of a software implemented input/output device, thereby eliminating the need for physical resources otherwise required for data communication between the stacks. First and second connection objects are built in the virtual device in association with the first and second stacks, respectively. An association is also built between the first and second connection objects, thereby enabling communication between the stacks via the first and second connection objects.

Abstract: An electrostatic motor comprising a stator and a rotor, one of which is equipped with a plurality of lands to which a voltage is sequentially applied. The other of the stator and rotor is made of conductive material. Rolling contact is established between the stator and rotor along at least one line of contact. The rolling contact is controlled to repetitive first and second paths along first and second surfaces of the stator and rotor, respectively, in which the lengths of the first and second paths are different. Embodiments include a cylindrical motor, a flexible disk motor and a conical motor.

Abstract: A logic circuit simulator for detecting a spike condition at the output of a simulated gate. A plurality of autonomous devices are arranged for parallel pipeline operation. Each device is designed to perform only a part of the overall simulation function. One of the devices is responsive to signals representing gate input stimuli and to gate propagation delay data primarily for performing the spike analysis function. Another device performs the function of gate output signal scheduling in response to gate input stimuli for transmitting messages containing said signals to the spike analyzing device and other devices of the simulator. When the spike analyzing device detects a spike condition, it transmits into the pipeline signals indicating the scheduling of an unknown output event on the gate in question.

Abstract: A method of partial scan design for chip testing and a circuit produced in accordance with the method in which the selection of scan memory elements eliminates cycles in the circuit while the circuit is in a test mode. Cycles are defined as feedback paths from an output of a memory element to an input of the memory element. Cycle length is the number of memory elements in a feedback path. Experimental data suggests that test complexity grows exponentially with the cycle length. By eliminating cycles of desired lengths, the set of scan memory elements may be only a small fraction of the total memory elements of a circuit.

Abstract: A computer system arranged for faster processing operations by providing a stack cache in internal register memory. A full stack is provided in main memory. The stack cache provides a cache representation of part of the main memory stack. Stack relative addresses contained in procedure instructions are converted to absolute main memory stack addresses. A subset of the absolute main memory stack address is used to directly address the stack cache when a "hit" is detected. Otherwise, the main memory stack is addressed. The stack cache is implemented as a set of contiguously addressable registers. Two stack pointers are used to implement allocation space in the stack as a circulating buffer. Cache hits are detected by comparing the absolute stack address to the contents of the two circular buffer pointers. Space for a procedure is allocated upon entering a procedure. The amount of space to allocate is stored in the first instruction. Space is deallocated when a procedure is terminated.

Abstract: A method of automatically identifying bitmapped image objects. Each of a set of templates in an object template library is compared with all areas of like size of a bitmapped image. A set of signals is generated for each such comparison that satisfies a defined matching criteria between the template and the image area being compared. The set of signals identifies the object based on the matching template, the location of the object in the image and an indication of the goodness of the match between the object and the template. A series of possible parse trees are formed that describe the image with a probability of occurrence for each tree. Each parent node and its child nodes of each parse tree satisfies a grammatical production rule in which some of the production rules define spatial relationships between objects in the image. The one of the possible parse trees which has the largest probability of occurence is selected for further utilization.

Abstract: A method of controlling congestion in a virtual circuit packet network. A initial packet buffer is assigned to each virtual circuit at each node into which incoming packets are stored and later removed for forward routing. If a larger buffer is desired for a virtual circuit to service a larger amount of data, then additional buffer space is dynamically allocated selectively to the virtual circuit on demand if each node has sufficient unallocated buffer space to fill the request. In one embodiment, the criterion for dynamic allocation is based on the amount of data buffered at the data source. In alternative embodiments, the criteria for dynamic allocation may be further based on the amount of data buffered at each node for a virtual circuit and the total amount of free buffer space at each node of a virtual circuit. Signaling protocols are disclosed whereby data sources and virtual circuit nodes maintain consistent information describing the buffer allocations at all times.

Abstract: Apparatus for directly converting thermal energy into rotational movement. A long shaft relative to its cross-section and made of an elastic material with a high thermal coefficient of expansion is equipped with a plurality of journals at prescribed points along its axial length. A corresponding number of fixedly mounted circular bearings receive the journals. The bearings are arranged to constrain the shaft into an elastic arc. Thermal energy is applied to all or a substantial part of the concave surface of the arced shaft. Means may be employed to force cool all or a portion of the convex portion of the arced shaft. As a result of this arrangement, the shaft elastically rotates about its axis within the bearings. Structure is disclosed for coupling the rotational movement of the shaft to a utilization device.

Abstract: An address matcher and process for same used as an aid in debugging computer programs. Each of a plurality of random access memories (RAMs) is addressed by a different subfield of a computer memory address so that each access of the computer memory also causes a read of each of the RAMs. Each RAM is programmed with encoded data to define upper and lower block addresses for that subfield of the computer memory address with which it is associated. An output circuit decodes the encoded data read from each of the RAMs as a result of a computer memory access and generates a signal if the computer memory address lies within the monitored address block.

Abstract: Apparatus for facilitating the transport and switching of synchronous and asynchronous digital data signals presented by data terminal or data communication equipments to a voice switching network such as a PBX advantageously without the use of modems. The clock rate of the PBX user's digital data is multiplied by a variable factor to define a synchronous transmission clock rate on a data link between a pair of interfaces, one locally connecting to the data terminal or data communications equipment and the other appearing as a port of the PBX switching equipment. The higher rate on the data link permits both the digital data as well as a control channel to be provided. Variations in the data terminal or data communications equipment clock rate do not affect the control channel. Variations in the voice sampling rate of switching modules serving different groups of ports through which the digital data is transported are accommodated.

Abstract: A parity checking arrangement for tag information in a cache memory. Parity generation is performed on the input tag in parallel with tag memory lookup and then compared with the parity stored in tag memory in order to speed operation. A single parity generator also may be used for writing into tag memory.

Abstract: A call message service arrangement in a telephone system. The arrangement automatically generates and stores a callback message for a called station responsive to a signal from a station served by the system that is associated with the call. If the arrangement is activated from the calling or called stations, a message is stored including the identity of the calling station. If the call has been redirected to another station for any reason, the identity of the other station or that of the calling station may be stored in the message responsive to different signals from the stations. Message waiting lamps are automatically lit and extinguished to alert called parties of the presence of stored messages.

Abstract: A data structure and search method for a data base management system. The structure and method allow the locating of a stored record in a massive system in a controlled and small number of mass memory accesses. The data structure is arranged into a plurality of search trees, each defining patent nodes and terminal nodes. The nodes of a tree are hierarchically arranged, and the trees are hierarchically arranged as a whole into levels. The initial search tree and an initial subset of trees, in some cases, are designed to be maintained in a main fast access memory. The remaining trees are kept in mass memory. A plurality of first storage files maintained in the mass memory are associated with terminal nodes of each of the trees except the final trees in the hierarchical structure. Terminating storage files, which are the ultimate repository for information, are associated with terminal nodes of the final trees.

Abstract: A tone receiver suitable for use in a telephone system and which adaptively narrows its amplitude sensitivity range defining valid tone signals on a per call basis in accordance with the amplitude of a first tone signal received on a call. The signal range adaptability improves signal echo rejection and spurious noise talkoff. A preferred embodiment is implemented by a programmed digital signal processor which increases the lower amplitude signal threshold in accordance with the amplitude of the first signal. An alternative embodiment adaptively attenuates the level of incoming signals before signal validation. A further improvement of both embodiments allows further amplitude range narrowing in response to any subsequent signal on a call which has an amplitude greater than that of any preceding signal in the call.

Abstract: Parity for the address of a low order zero in an input data word is generated directly from the input data rather than from the address of the low order zero. A find low order zero circuit (11) generates an address of the low order zero in the data word. Simultaneously with this operation a parity generating circuit (12) operates on the input data word to generate parity for the low order zero address. The parity generating circuit comprises a plurality of individual circuits (30 through 33) each of which operates on a different byte of the input data word. The individual circuits each generate a control signal (E.sub.a,E.sub.b . . . ) according to whether or not its byte contains a low order order zero, and a result signal (R.sub.a,R.sub.b . . . ) which represents the parity of the address of the low order zero, if any, in the byte taking into account the byte position in the input data word. Logic circuitry combines the control and result signals to form the overall parity for the low order zero address.

Abstract: An arrangement in a telephone system providing for the handling of calls which have been automatically redirected to a call covering station in a customer premises telephone system. The covering station is equipped with one or more function buttons each for activating a different call processing function on a covered call at the covering station. The arrangement automatically identifies the intended principal station on a covered call and performs the necessary operations associated with an operation of one of the function buttons with respect to the principal station in question regardless of how many principal stations are covered by the covering station, thereby eliminating direct station selection (DSS) keyfields or the dialing of principal station numbers from the covering station.

Abstract: A call coverage arrangement in a telephone system. Any station served by the system may be assigned to a call coverage group as a principal station. A coverage group includes the identities of a plurality of call covering stations for the principal station and an indication of the order of preference of the covering stations. Call coverage criteria are stored for principal stations specifying circumstances under which calls intended for the principal stations are redirected to coverage. A covered call is redirected sequentially to each of the covering stations in a coverage group in the order of preference until the call is answered or abandoned. The coverage criteria include options based on both the state of a principal's station (active, busy, idle, etc.) and the class of an incoming call (internal, external, priority). Principal stations are equipped with a "send all calls" button.

Abstract: A time division multiplex (TDM) switching network is disclosed in which at least part of the network comprises a space switching portion (TMS) and in which the need for duplication of the space switching portion, and like methods of achieving network reliability, is eliminated. Data from an incoming channel is partitioned into successive blocks, a prescribed number of which form a set of blocks. The blocks are of predetermined size. Each of the blocks of a set is switched via different paths of the space portion of the network. A single network fault can therefore cause the loss of only one block of data in a set. This loss can be made insignificant in the case of data representing telephone conversations. For data not representing telephone conversations, error checking and correcting information is added to the set before transmission through the space portion of the network and errors occurring during transmission are corrected thereafter.

Abstract: A microprocessor system that provides protection against memory violations by interrupting the central processing unit (CPU). A problem arises when the interrupt itself causes memory violations in push-down stack operations. This problem is solved by providing an auxiliary memory to store stack overflow data. Memory violations are detected (30, 40) and overflow data is written (42, 60, 33, 100) into auxiliary memory, at sequential locations (50, 51, 60). An interrupt signal is returned (30, 20) to the CPU. A stack overflow interrupt program reads the number of locations written (50, 80, 90), and accesses the auxiliary memory (100, 60, 70, 90) to determine and correct the cause of the overflow.

Abstract: Frequency encoded signaling method and structure to correct for frequency error introduced in the generation of encoded signals. A sequence of frequency encoded signals are recorded on rotating magnetic recording devices in telephone offices in conjunction with recorded announcements. The signals identify the types of announcements. Speed variations in the different recording devices introduce frequency errors in the reproduction of the signals, hindering their automatic decoding. This problem is solved by recording a reference frequency signal with the encoded signals on the recording devices. A receiver detects the signals and measures the difference between the expected reference signal frequency and the received reference signal frequency.