Abstract: An ATM switching arrangement in which two types of cells are distinguished. A first type of cells is marked as low loss cells and a second type of cells is marked as low delay cells. In the switching arrangement a cell buffer (9) is subdivided into a first memory area (LL) for the low loss cells and a second area (LD) for the low delay cells. In the case of the cell buffer (9) being completely filled, low loss cells get read-in priority over low delay cells. In reading out from the cell buffer low delay cells take priority over low loss cells, unless the low delay area is empty. It is also possible to set a threshold value for the content of the low loss area; when the content of the low loss area exceeds the threshold value outputting of the low loss cells can then be started.
Abstract: A frequency-modulated digital signal demodulator includes a digital quadrature filter having n elements arranged in cascade, each delaying the input signal by a value T.sub.E =1/F.sub.E, where F.sub.E is the sampling frequency, a number of channels arranged in parallel with the cascade arrangement of delay elements, each channel having a multiplier for multiplying by a given coefficient, a first and a second summing circuit for summing the respective output signals of said multipliers, the output signals of the two summing circuits constituting the quadrature output signals of the filter and being referred to as reference and phase-shifted signals. At the output of the filter a circuit for calculating the instantaneous phase .phi..sub.n of successive signal samples is provided.
Abstract: A sub-assembly (20) of a housing for electronic equipment and which is capable of carrying electronic components. The sub-assembly (20) comprises an injection moulded plastics body having an area (21) in which a regular array of apertures (22) are formed, pushbuttons (23) being mounted in each aperture of the regular array of apertures. The pushbuttons (23) are shaped and dimensioned so that they cover the whole of the first area (21), the gaps between the pushbuttons (23) being limited to those required to allow clearance for operation of individual pushbuttons (23). Some of the pushbuttons are replaced by cover plates (24,25) which are mounted in appropriate apertures of the array of apertures.The pushbuttons (23) operate on dome shape elastomeric switching elements (45) arranged between the pushbutton plungers (43) and the printed circuit board (40). The domes have an electrically conductive portion which bridges conductive tracks on the printed circuit board when the corresponding pushbutton is depressed.
Abstract: A complementary Silicon-On-Insulator (SOI) Lateral Insulated Gate Rectifier (LIGR) is fabricated in a monocrystalline silicon layer provided on a major surface of a substantially insulating substrate. The monocrystalline silicon layer includes a number of adjacent, doped coplanar layer portions, with the complementary SOI LIGR device being formed of adjacent, contacting layer portions forming two complementary LIGR elements with a common source region. The common source region, as well as both of the drain regions of the device, are composed of regions of both the first and second conductivity types. In this manner, a simple, easily fabricated, balanced, high performance complementary LIGR structure is obtained in which undesired substrate currents are substantially eliminated.
Abstract: In a binary counter made using the I.sup.2 L technique, the realization of different gate types is complicated, because only NAND gates can be obtained directly. According to the invention, a particular circuit construction is indicated, which is constructed according to the I.sup.2 L technique, is very simple and requires only a few gate transit times so that a comparatively high switching speed can be attained. In the circuit construction of the invention, both the flipflops and their associated combinatorial networks are fabricated in the I.sup.2 L technique, using only NAND gates. Nevertheless, because of the particular circuit configuration of the invention, all of the necessary internal signals can be generated in an efficient manner.
Abstract: The invention relates to a semiconductor device of the hetero-junction transistor type comprising a stack of semiconductor layers which in combination constitute the source, drain and gate regions, while the current path between the source and drain regions is substantially at right angles to the various junctions. The gate region constitutes an electron accumulation region in the form of a two-dimensional quasi Fermi-Dirac gas which can be brought to the desired polarization potential of at least one gate electrode, while the electrons forming the source-drain current traverse this electron cloud without having a strong interaction with it, in ballistic or quasi-ballistic conditions.
Abstract: The invention relates to a matrix of light-emitting diodes and a method of manufacturing same. A matrix comprises highly doped contact lines of a first conductivity type, localization zones of the second conductivity type opposite to the first type extending transversely with respect to the semi-insulating zones arranged along lines and/or columns and separating along diodes an active layer in contact with the contact lines and a superficial injection layer. The contacts connect the diodes columnwise, regions being internally limited along lines by the area straight above the upper parts of the localization zones, and along columns by the semi-insulating regions. Thus, the contacts are entirely situated outside the light emitting zones defined by the localization zones. The method of manufacturing utilizes steps of localized etching and epitaxy.
Abstract: An elementary decoder circuit for a monolithically integrated static random access memory is constructed by means of gallium arsenide field effect transistors and formed by a NOR-gate whose n inputs receive the n coded addressing signals a.sub.1, a.sub.2, . . . , a.sub.n of the memory, or their complements, and whose output supplied a signal which is applied to the upper transistor of a push-pull stage as well as a complementary signal, obttained via an inverter transistor, which is applied to the lower transistor of the push-pull stage.
Abstract: A ring-shaped TDM digital communication system and method for enabling stations connected thereto to obtain access to a common message channel available for all of the stations. Access is unambiguously determined by an arbitration procedure which selects the station which obtains access to the message channel and excludes all other stations. Such message channel is also used for the arbitration procedure, which is based on recognizing the channel as being unoccupied if the value of the information in a time slot field thereon remains the same in successive cycles around the ring of a TDM frame comprising such field. The messages which are transmitted are structured so that error detection and correction, addressing, congestion indication, etc., can easily be included.
Abstract: An electromagnetic deflection unit for a television picture display tube, the deflection unit being arranged around the envelope of the display tube and comprising a first deflection coil and a second deflection coil located more closely to the display tube envelope than the first deflection coil and coaxially therewith. An annular core of magnetizable material encloses groups of conductors of both the first and second deflection coils. An additional annular core of magnetizable material encloses groups of conductors of only the second deflection coil, being placed around the portion of such coil which extends beyond the end of the first deflection coil in the direction toward the display screen of the display tube. The mutual locations of the dipole fields produced by the deflection coils thereby reduce north-south raster error.
Abstract: Semiconductor devices including one or more gate-controlled unipolar hot-carrier transistors have a semiconductor barrier region located between laterally-separated first and second region portions of one conductivity type. The barrier region has a net doping concentration of the opposite conductivity type and is sufficiently thin such that the depletion layers formed at zero bias with both the first and second regions substantially merge together to deplete the barrier region of mobile charge carriers. Current flow between the first and second region is at least partially by thermionic emission of charge carriers of the one conductivity type across the barrier region at a major surface of the body. The transistor has a gate in the vicinity of the barrier region and capacitively coupled thereto (for example via a dielectric layer) so as to permit the thermionic emission current to be controlled by applying a voltage to the gate to adjust the effective barrier height of the barrier region.
Abstract: A semiconductor device has a surface zone which forms a planar pn junction with the surrounding substrate, this pn junction being biased in operation in the reverse direction. In order to increase the breakdown voltage, one or more floating zones are located beside the pn junction within the range of the depletion zone, which also form planar pn junctions with the substrate. According to the invention, the floating zones have an overall doping of at least 3.multidot.10.sup.11 and at most 5.multidot.10.sup.12 atoms/cm.sup.2, as a result of which they are substantially depleted at a high reverse voltage.
Abstract: The frequency of a voltage controlled crystal oscillator is conventional pulled by means of a varicap diode forming the load capacitance of the oscillator crystal. In order to realize a wider range of frequency pulling, the load capacitance 44 is alternately switched on and off in a known manner. According to the invention a band-switch diode 46 is utilized as a switch element, the hole-storage time of this diode being as long as or longer than the oscillator cycle. By applying a low-frequency control voltage to the diode it is rendered self-switching within the oscillator cycle, so that proportional frequency tuning is achieved.
Abstract: A circuit for extracting the square root of a 2n-bit input binary number. The circuit comprises n successive subcircuits, the m.sup.th such subcircuit consisting of (m+1) add/subtract cells, where 1.gtoreq.m.ltoreq.n. The successive subcircuits process successively less significant pairs of bits of the input number, such bits respectively being received on a data input of two respective add/subtract cells in each subcircuit. Such cells receive a logic bit "1" on a second data input and a logic "0" on a control input thereof, and so always operate in the addition mode. The remaining add/subtract cells of any m.sup.th subcircuit are controlled by the carry signal which constitutes the output of the (m-1).sup.th subcircuit. The root extraction circuit thereby effects subtraction by 2's complement addition, avoiding the need for inversion of any data input signals. That achieves a completely regular circuit pattern permitting more efficient use of chip area when the circuit is realized in integrated form.
Abstract: A loudspeaking telephone instrument comprises a transmit path comprising a microphone (1) and comb filter (2); a receive path comprising a comb filter (3), a frequency shifter (4) and a loudspeaker (5); and a hybrid circuit (6). The frequency shifter (4) shifts the frequency of a signal applied to its input by a fixed amount and the comb filters (2,3) are arranged so that the frequency shifted signal falls in their stop bands. This increases the available gain in the loudspeaking telephone instrument before instability occurs. The spacings of the pass and stop bands of the comb filters (2,3) are at a multiple of the frequency by which the frequency shifter shifts that of its input signal.
April 22, 1987
Date of Patent:
May 31, 1988
U.S. Philips Corp.
Ian Phillips, Lawrence J. Hibberd, Leslie H. Williams
Abstract: A central exchange comprising at its input end a change-over arrangement having a change-over switch for each input line and at its output end a change-over arrangement of an identical structure having a change-over switch for each output line, which are controlled in parallel. Each change-over switch sequentially supplies at its output the channels of a multiplex frame on the different input lines. For each input line a data store and a control store are assigned to the change-over switch at the input end, in a predetermined sequence for each instant, each data store storing the words of all channels of always one input line, but always a different frame. Consequently, all the data stores together contain the words of all the input lines from a number of consecutive frames equal to the number of input lines. The control stores have the same number of addresses as the data store and address these addresses in a similar way, but always shifted through one frame length from data store to data store.
November 12, 1986
Date of Patent:
May 31, 1988
U.S. Philips Corp.
Johann E. W. Kruger, Wolfgang E. Jasmer
Abstract: A color display tube deflection unit having an annular magnetizable core of tapered cylindrical shape and a raster distortion correction device comprising four pole shoes positioned at the corners of a rectangle adjacent the end of the core facing the display screen, the pole shoes respectively being near respective ends of a pair of vertical deflection coils. The four pole shoes are connected in pairs by respective bridging flux collector elements of soft magnetic material. The flux collector elements divert magnetic flux from the core which otherwise would not have emerged from the core, and such flux is conveyed to the pole shoes so as to cause the vertical deflection field to become pincushion-shaped adjacent the display screen.
Abstract: A flat cathode ray display tube in which an electron beam (30) is directed firstly in a rear region (24) parallel to a faceplate (14) carrying a phosphor screen (16) and then reversed to travel in the opposite direction in a front region (22) before being deflected towards, and raster scanning over, the screen. A magnetic shield (60) is provided in the rear region to shield the beam from magnetic fields entering through the faceplate over a portion of its path length in that region to reduce raster shift effects caused by such fields. This is especially useful when the electron beam in the front and rear regions is a low-energy beam, rendering it particularly susceptible to influence by magnetic fields, such beam being supplied to an electron multiplier (44) overlying the screen.
Abstract: A data transmission system for providing error protection of transmitted data words. The less significant bits of a data word are, by means of matrix multiplication, encoded into a first redundant proto-code word and the more significant bits are, by means of further matrix multiplication and delay by different word recurrence intervals encoded in a set of further redundant proto-code words. A composite of the proto-code word is formed by means of a modulo-2-addition of code words, so that for the less significant data bits a block code is realized, while for the more significant data bits a convolutional encoding is realized. In the decoding, the more significant bits of the composite code word are decoded by means of Viterbi decoding, the Viterbi metric being determined from the deviation between the reconstructed contribution of the less significant bits to such code word and the actually received contribution of such bits to such code word.
Abstract: A pulse-width modulator comprising a square-wave generator which triggers a monostable multivibrator driven by a controllable constant current source, the multivibrator having a capacitor as a timing element. The output of the multivibrator controls a gate circuit to which the square wave is also applied, thereby controlling the width of the square wave output from the gate circuit. The modulator can be assembled from standard CMOS building blocks and several external components, thereby achieving a power dissipation below 10 mW. If the current source is controlled by a CMOS variable-gain amplifier, the modulator can serve as the control circuit of a clocked direct voltage converter having internal losses below 25 mW.