Abstract: A method apparatus for finding and assigning both commercially valuable and vanity (CSV) numbers in a telecommunications system that permits number portability. CSV Numbers are identified by a rules based process that combs the unused number database for valuable combination and saves those numbers in a special database. Those numbers that are not so identified stay in the unused database for general assignment. To assign a CSV number, a similar process is used to generate candidate numbers based on a desired keyword, and then the candidate numbers are used to query the special database and even the general unused number database to get available candidates. The available candidates are offered to the requesting user and the user may accept or decline.

Abstract: A method and apparatus for very low, in some case even zero, data latency accesses to a shared resource for devices such as disk drives and their channel formatting agents. The method and apparatus together will controllably terminate any non-low-latency access in process and then start a low latency access. Since the computer system has a group of three agents that may require low latency accesses, a special low latency arbitration method and apparatus is provided instead of the normal dynamic time loop arbitration. The low latency arbitration is call zero latency loop arbitration. The method and apparatus can actually provide zero latency data accesses for disk reads and writes in many cases. Once all low latency accesses are fulfilled, the method and apparatus allow the computer system to return to its slower, normal dynamic timed loop arbitration.

Abstract: A SCSI disk controller integrated circuit (SDC IC) provides much of the hardware necessary to perform asynchronous data transfers between a SCSI host bus and a disk interface circuit through two on-chip rotating buffers. The SDC IC is designed to be used in conjunction with a microprocessor and a stored microprocessor program. The SDC IC with its numerous registers reduce external parts by allowing some of the SCSI disk controller functions to be performed in software rather than hardware. On-chip sequence controllers and the rotating buffers of the SDC IC help the microprocessor to separate the control functions and the data transfer functions in order to maximize data transfer throughput. By arranging the control registers, the rotating buffers, and the sequence controller on a single integrated circuit a high performance, compact and inexpensive disk controller can be built using the SDC IC, a microprocessor and a small number of additional integrated circuits.

Abstract: An electrical short-circuit monitoring arrangement for a three-phase motor, including its supply lines, whose speed is controlled by a constant-current d.c.-link converter. The harmonic ripple voltage superimposed on the motor voltage generated as a consequence of the commutation by the constant-current d.c.-link converter at the output of the converter is determined, filtered, and supplied to a phase-monitoring unit, which when dropping below a selected amplitude variable of the harmonic voltage of at least one phase, triggers the switching module whose switching mechanism activates a disconnect switch to interrupt the motor circuit upon occurrence of a switchoff signal.