Abstract: A boundary-scan circuit for a bidirectional pin of an integrated circuit which uses fewer standard cells if a cell design is considered, or fewer devices if non-standard cell integrated circuits are considered. In either case, the present invention provides the same functionality as provided in of the bidirectional boundary-scan circuits shown in TEEE 1149.1 in a circuit that should be more compact for the same logic family and integration technology.

Abstract: A boundary-scan circuit method and apparatus for asserting an internal reset signal connected to core logic circuits of an electronic device in order to assure that testing will begin and end in a safe, known logic state. A safe end state is assured even if the system reset signal on an input pin of the electronic device is logically disconnected from the internal reset connection to the core logic, as often occurs in boundary-scan and related testing.

Abstract: A method and apparatus for providing coherency for cache data in a multiple processor system with the processors distributed among multiple independent data paths. The apparatus includes a set of cache monitors, sometimes called snoopers, associated with each cache memory. There are the same number of monitors as there are independent data paths. Thus, each cache stores cache tags that correspond to its currently encached data into each of the monitors of the set associated therewith. Thus, each cache has an monitor associated therewith which monitors each of the multiple paths for an operation at an address that corresponds to data stored in its cache. If such an access is detected by one of the set of monitors, the monitor notifies its cache so that appropriate action will be taken to ensure cache data coherency.

Abstract: An actuator mechanism which is located at the front of an electronic unit and converts the push-on, push-off action of a switch to a sliding action. By converting the actuating action from an in-and-out pushing motion to a transverse sliding motion, inadvertent actuation of this switch is all but eliminated. This conversion is provided in a simple, cost effective mechanism.

Abstract: A circuit for use with a SCSI interface for controlling synchronous data transfers into an attached FIFO memory. The circuit uses a comparator to keep track of the number of FIFO locations available by starting with a threshold value, which represents the locations available initially, and comparing the net number of FIFO locations filled to the threshold value. The net number of FIFO locations filled is kept by a counter which counts the difference between the words transferred into the FIFO and the words transferred out of the FIFO. The threshold value is an adjusted offset value if the SCSI interface is operating in INITIATOR mode, and the FIFO size if the SCSI interface is operating in TARGET mode. When the comparator determines that the FIFO is filled, it pauses the current synchronous message by withholding an ACK in the INITIATOR mode or a REQ in the TARGET mode.

Abstract: A pseudo-static ROM circuit which uses cross-coupled sense amplifiers to provide rapid accesses to ROM stored data, yet because of a special bit line precharger and dummy load arrangement dissipates very little static power. After a stable logic static is attained by the sense amplifier during a READ, the sense amplifier and the precharger-dummy load circuits do not draw any appreciable current or power until the next precharge-and-READ operation is initiated. Therefore, almost all of the power dissipated by the pseudo-static ROM occurs during the dynamic operations of precharging and READing the bit lines.

Abstract: A look-ahead method and apparatus for monitoring the number of bytes in a FIFO memory. The apparatus uses look-ahead techniques to determine all possible results and then selects the appropriate result from all of the possible results to update a byte count register. The selection is based on the number of bytes READ and the number of bytes WRITTEN during a FIFO memory cycle. This look-ahead method and apparatus provides a definite time advantage over known FIFO monitoring systems that perform an addition or subtraction with the READs and WRITEs at the end of each FIFO cycle, and then use the arithmetic result to update a byte count register.

Abstract: A single transformer converter which may switchably disconnect all of its converter outputs, or alternatively just some of the converter outputs. In some electronic systems this would allow the turning-off of some units, such as printers, while leaving on other units, such as a CPU or a twenty-four hour clock. Further, an uninterruptible output is provided by the converter to maintain applications and operating systems software stored a CMOS RAM even in the event of a power outage.

Abstract: The multiplexing character processor of the present invention multiplexes data characters to and from a plurality of communication lines to a Central Processing Unit by bit slicing. Input data present on the plurality of communication lines is sampled at a rate which is at least 16 times the data bit rate and is formulated as a serial data bit stream. Each sample corresponds to a time slice which slice is allocated to a given communication line under the control of a scan list. A high data rate communication line can be placed on the scan list more than once to insure accurate data reproduction. Character assembly and disassembly is performed in an arithmetic logic unit (ALU) under program control, to provide the flexibility to support various communication link protocols. The input data on each communication line may have a different protocol. Synchronization of the serial data bits to the communication lines is performed by a data bit synchronizer DBS.

Abstract: In a pipeline data processing system, a method for additively converting an address expressed in offset form to a corresponding real address in main memory (assuming that such address exists in main memory). Because of the pipeline data processing design, this offset address can be accessed from main memory in the same amount of time required by a non-offset, real address. An apparatus for practicing this method is also provided. This method and apparatus will perform the functions usually performed by a translation table or similar device in virtual memory systems. Furthermore, it will perform those functions faster and will utilize a smaller integrated circuit area than translation table type virtual memory systems.

Abstract: An architecture for generating a hardware cursor in the context of a bit mapped video display system operable from a frame buffer with non-displayed but addressable memory space. A segment of the non-displayed memory is loaded with cursor information controlling the generation of its outline and its color pattern. When accessed, this cursor control data is accessed from the non-displayed segment of the memory during each horizontal blank time preceding the raster scan of the video pattern data subject to cursor overlay. Location of the cursor within the video display is determined by a group of position registers which are loaded by the CPU with cursor position data during the vertical blank time. The position registers in conjunction with a group of counters coordinate the insertion of the cursor data into a byte stream of display data as it makes its way to the CRT screen. This display data is stored in the frame buffer and is transferred to the pixel output buffer.

Abstract: An overcharging of a back-up battery through a protection diode of a first power regulating FET is prevented by adding a second power regulating FET that is equivalent to the first FET and the second FET has its source and drain connections reversed. By connecting and operating the second FET in a reverse direction from the first FET, the forward current direction of the protection diode of the second FET is opposite to the forward current direction of the protection diode of the first FET. Thus, the power regulator will always have one of the protection diodes reverse biased, thereby preventing reverse overcharging through the diodes. A power regulator using two such power FETs in series to prevent reverse overcharge current has a lower ON impedance than only one power FET that is in series with a blocking diode, and thereby provides more usable voltage and current for back-up situations.

Abstract: A synchronizer which samples and stores the synchronized data with a transparent latch instead of a flip-flop or similar device to avoid the long set-up times required by such devices. The synchronizer compares its input level to its output level. When they are found to be different because of an input data change, the difference is used to gate the system clock, which in turn gates the transparent latch to sample and store the changed input data level as the new data output level. Since the change in the input data gates the system clock which further gates the opening of the latch, the input data is essentially guaranteed to fulfill the latch set up time requirements. For the difficult case when the input data change occurs as the clock is changing states, a Schmitt trigger is inserted ahead of the latch gating input. The Schmitt trigger will either respond and provide a proper pulse width and magnitude to drive the latch without metastability, or it will pass a "runt pulse" and not respond to it.

Abstract: A boundary scan test circuit for inclusion into ASIC and or VLSI circuits which does not require any additional pads/pins to support full boundary scan functionality. The invention uses the power and capability of existing address and data buses to transfer test data into the integrated circuit under boundary scan test, and uses the same buses to transfer test results out of the integrated circuit under test to be interpreted by the test processor of the system.

Abstract: A compact and inexpensive height adjustable base for a video display. The invention provides height adjustment while maintaining a constant screen orientation with respect to the horizontal. This base is designed for a seated user. It keeps the footprint of the base to a minimum, and by proper shaping, allows most keyboards to share some of its footprint area. The minimum height is only slightly higher than the height of non-adjustable bases, and the maximum height is selected to provide a convenient height for viewing by operators of any stature, and to keep the structural requirements of the stress bearing components low. By keeping the structural requirements low, the material and assembly costs may be kept low, leading to a cost effective height adjustable base.

Abstract: An arbitration circuit especially useful for SCSI-II applications, but also having other applications. The basic arbitration circuit requires only thirty NOR gates, one inverter, and connection to all but the lowest priority data line in order to have an arbitration circuit for sixteen lines. The basic circuit will arbitrate among up to sixteen units and is extremely compact and could be used on SCSI related integrated circuits in addition to other SCSI circuitry. The basic arbitration apparatus may also be expanded to accommodate a thirty-two line SCSI-II bus by extending the number of stages to thirty-two.

Abstract: A monitor device connected between a pin for connection to the more positive lead of the voltage supply or the less positive voltage of the power supply and the more positive voltage supply conductors or the less positive voltage supply conductors on the integrated circuit substrate. The monitor circuit has a threshold circuit so insignificant perturbations will not trigger the monitor. The monitor circuit also has a reference voltage input such that the same circuit may be used for the more positive side of the power supply, as well as, the less positive side with straightforward modifications. When the monitor circuit detects a significant fault, i.e. one that could falsely switch part of the integrated circuit, it sets a flip-flop to record such an occurrence. The monitor flip-flop cannot be reset by the usual reset signals, in order to prevent it from being cleared by normal diagnostics and error recovery operations.

Abstract: An special arrangement of the magnetic components of a horizontal sweep output circuit to reduce the net flux density and magnetic induction that are present at the exterior of a video display. The special arrangement meets the new, lower VLF electro-magnetic emission standards of some of the European countries, such as Sweden. The method used for obtaining this special arrangement of horizontal sweep output components is also disclosed.