Abstract: An illumination system is described that efficiently produces linear polarized light for use in LCD projection. A polarizing beam splitter and half-wave retarder plate produce two adjacent collimated beams of light having a common polarization direction. These adjacent beams are spatially integrated into a single collimated polarized beam whose aspect ratio is subsequently converted to match that of the LCD format.

Abstract: A method of providing instructions and data values to a processing unit in a multi-processor computer system, by expanding the prior-art MESI cache-coherency protocol to include an additional cache-entry state corresponding to a most recently accessed state. Each cache of the processing units has at least one cache line with a block for storing the instruction or data value, and an indication is provided that a cache line having a block which contains the instruction or data value is in a "recently read" state. Each cache entry has three bits to indicate the current state of the cache entry (one of five possible states). A processing unit which desires to access a shared instruction or data value detects transmission of the indication from the cache having the most recently accessed copy, and the instruction or data value is sourced from this cache.

Abstract: A method of changing the functionality of a statically bound device driver, by dynamically extending the static device driver using a registered driver extension. The static device driver has a plurality of handlers or functions (such as input/output functions) used to control a device that is connected to or part of the computer system, and the driver extension modifies at least one of these functions, although it can be used to change several, or even all, of the functions. In the embodiment wherein the computer system is a UNIX-type workstation having a kernel residing in the memory, the static device driver is loaded in the kernel and is dynamically extended by providing at least one entry point for the driver extension.

Abstract: A method of providing programmable congruence classes in a cache used by a processor of a computer system is disclosed. A logic unit is connected to the cache for modifying original addresses of memory blocks in a memory device to produce encoded addresses. A plurality of cache congruence classes are then defined using a mapping function which operates on the encoded addresses, such that the logic unit may be used to arbitrarily assign a given one of the original addresses to a particular one of the cache congruence classes. The logic unit can modify the original addresses by setting a plurality of programmable fields. The logic unit also can collect information on cache misses, and modify the original addresses in response to the cache miss information.

Abstract: A phase/frequency detector, such as may be used in a phase-lock loop (PLL), having reduced jitter at high frequencies by reducing or eliminating the dead zone. The detector generates two output signals (UP and DOWN) wherein one of the output signals (depending upon which input signal arrives first) has a pulse width which is equal to a time delay between the input signals. There is a dead zone associated with very small phase differences between the input signals, and the dead zone is reduced by increasing the durations of two output pulses, using several delay elements which operate on signals that are derived from the reference and feedback inputs. The circuit may be tuned to reduce the dead zone to less than one picosecond, making it particularly useful for very high speed (greater than one gigahertz) clock circuits. The phase/frequency detector uses self-resetting, complementary metal-oxide semiconducting (SRCMOS) gates.

Abstract: A method of providing programmable associativity in a cache used by a processor of a computer system is disclosed. A congruence class of a memory block is defined using a first mapping function, providing a first associativity level of the cache. A logic unit connected to the cache monitors cache misses as the cache uses the first associativity level, and selects other associativity levels based on the cache misses, using other mapping functions. The logic unit has incorporated therein means for selecting the other associativity levels based on a rate of the cache misses in a particular congruence class. The congruence class may be defined by associating the memory block with a particular set of cache blocks in the cache, based on a first portion of an address of the memory block, and the other mapping functions may be implemented by dividing the particular set into subsets and selecting a subset for the memory block based on a second portion of the address.

Abstract: A monitor within an integrated circuit is disclosed for providing a signal which is proportional to an integrated circuits operating environment. A differential gain cell within the integrated circuit is biased with a bias circuit. A first environment sensitive circuit provides a signal to the first input of the differential gain cell and a second environment sensitive circuit provides a signal with a known relationship to the first environment sensitive signal to the second input of the differential gain cell. The signal produced by the second environment sensitive circuit has a known operational relationship with the signal produced by the first environment sensitive circuit such that changes in the integrated circuit operating environment produce a deviation between the two signals. The differential gain cell in response to the signal received on its first input and second input produces a signal which is responsive to the operating environment of the integrated circuit.

Abstract: A method of improving operation of a cache used by a processor of a computer system by introducing a level of randomness into a replacement algorithm used by the cache in order to lessen "strides" within the cache is disclosed. Different levels of randomness may be introduced into the replacement algorithm at different times to optimize the cache for different procedures running on the processor. The level of randomness can be selectively introduced by using a basic replacement algorithm to select a subset of a congruence class, and one or more random bits are then used to select a specific cache block within the subset for eviction. The basic replacement algorithm can be a least recently used algorithm. There may be three levels of randomness for a 4-way set associative cache, and there may be four levels of randomness for an 8-way set associative cache.

Abstract: Provided is a mechanical structure, for an information handling unit in which are included one or more exchangeable electric components, whose interior is enclosed by a box. The box has: an exchange opening formed for a replacement of an exchangeable electric component; and a lid for engaging the exchange opening and for contacting the exchangeable electric component. According to the present invention, the heat releasing effect can be enhanced with no deterioration of the ease with which a heat generating component can be exchanged. In addition, the present invention can be embodied as a relatively simple mechanical structure, and manufacturing costs can be reduced.

Abstract: An interface cable which allows access to an operational Peripheral Component Interconnect (PCI) bus compatible circuit board is disclosed. A flat flexible cable (30,72) secures a plurality of connectors (50,32,36,38) at substantially equal intervals. The connectors on the flat cable are adapted to receive a connection (62,63,64,66,68) on a first edge of the PCI compatible circuit board (82,90). When the PCI compatible circuit board is plugged into the flat flexible cable, a second edge of the PCI compatible circuit board which is opposite the first edge is free to move laterally, away from neighboring circuit boards in response to a flexing of the flat flexible cable. Open space is created adjacent to the PCI compatible circuit board allowing sufficient access to surfaces of the functioning PCI compatible circuit board for testing purpose.

Abstract: A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. After a value (data or instruction) is loaded from system memory into a cache, the cache is marked as containing an exclusively held, unmodified copy of the value and, when a requesting processing unit issues a message indicating that it desires to read the value, and the cache transmits a response indicating that the cache can source the value. The response is transmitted in response to the cache snooping the message from an interconnect which is connected to the requesting processing unit. The response is detected by system logic and forwarded from the system logic to the requesting processing unit. The cache then sources the value to an interconnect which is connected to the requesting processing unit. The system memory detects the message and would normally source the value, but the response informs the memory device that the value is to be sourced by the cache instead.

Abstract: An improved pointer device, such as a mouse, for a computer system having a video display that uses a moving graphical pointer. The pointer device has switches or dials that allow independent adjustment of mouse speed and acceleration. Separate adjustments can be made for X and Y axes of motion of the mouse. Since the adjustment functionality is built into the hardware of the mouse, the mouse user is able to easily configure mouse behavior without navigating various menus and panels in software drivers, providing functionality which may not otherwise be available on the user's system.

Abstract: A method of bypassing defects in a cache used by a processor of a computer system. A repair mask has an array of bit fields corresponding to cache lines in the cache, and when a particular cache line in the cache is identified as being defective, a corresponding bit field in the repair mask array is set to indicate that the particular cache line is defective, and further access to the defective cache line is prevented, based on the corresponding bit field in the repair mask array. The repair mask can be used to prevent the defective cache line from ever resulting in a cache hit, and to prevent the defective cache line from ever being chosen as a victim for cache replacement. Using a set associative cache, the defective cache line is thereby effectively removed from its respective congruence class. This approach allows the cache to use all non-defective cache lines without any cache lines being reserved for redundancy.

Abstract: A method of using a debugger for a computer operating system by providing a statically bound debugger driver which can be used early in the boot process, and further providing one or more dynamic debugger drivers which can be loaded after system initialization. The core portion of the operating system, such as the kernel for a UNIX-type workstation, makes a determination of whether any hardware device is connected to the computer that is of the type of debugger devices supported by the statically bound driver; if so, then the debugger can be used early in the boot process, but if not, provision is made for calling the dynamic debugger driver from some other portion of the operating system software, such as from the boot filesystem or PAL. The dynamic debugger driver may be selected from a plurality of dynamic debugger drivers, the particular selected dynamic debugger driver being associated with the particular hardware device that is actually connected to the computer.

Abstract: A method of detecting errors in a data stream being transmitted in a computer system, e.g., from a memory array to a memory controller, by determining whether the encoding was performed using a first encoding method or a second encoding method, and thereafter decoding the data stream using a logic circuit based on a single parity-check matrix. The entire parity-check matrix is used to decode the data stream if the first encoding method was used, and a subset of the parity-check matrix is used to decode the data stream if the second encoding method was used. Encoding according to the first method allows correction of all single-symbol errors and detection of all double-symbol errors in the data stream, and encoding according to the second method allows correction of all single-bit errors and detection of all double-bit errors in the data stream. The subset matrix may be permuted if the second encoding method was used, to create a permuted matrix further allowing detection of single-symbol errors.

Abstract: A data processing system for managing a plurality of objects within said data processing system, the distributed data processing system having an object oriented environment. A container object is created for holding objects and a plurality of objects is detected within the data processing system. A filter object is associated with the container object, wherein the filter object receives the plurality of objects within the data processing system and the filter object passes selected ones of the plurality of objects to the container object. The data processing system is periodically monitored to detect changes in the plurality of objects. The container object is automatically updated using the filter object to pass selected ones of the plurality of objects to the container object in response to monitoring the data processing system, wherein the container object is automatically updated.

Abstract: A data storage device for a computer system, such as a hard disk drive (HDD), provides means for channeling air flow from the spinning disks to other components within the HDD enclosure that require cooling, particularly a voice coil motor having a coil which is used to move an actuator assembly. Channeling may be provided by forming a slot or gap in the disk cavity wall, or by providing an insert part which has a channel formed therein that directs air flow to the VCM coil.

Abstract: A computer system having an improved method of handling interrupts associated with I/O operations to reduce interrupt latencies. The computer system includes one or more processing units, a memory device (e.g., RAM) connected to the processing unit via a system bus, and a plurality of I/O devices providing interrupt sources, connected to the processor via an I/O bus and a bus bridge. The bus bridge has incorporated therein or connected thereto means for intercepting interrupt requests transmitted to the processing unit and handling the interrupt requests without suspending the current process in the processing unit. In the preferred embodiment, the means for intercepting and handling the interrupts includes a storage device or array having pico-code instructions which are scheduled for execution in a sequencer by the interrupt control logic. If the pico-code sees an interrupt that it is not programmed to handle (such as an exception), it can pass that interrupt to the appropriate processing unit for handling.

Abstract: A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. After a value (data or instruction) is loaded from system memory into a plurality of caches, one cache is identified as a specific cache which contains an unmodified copy of the value that was most recently read, and that cache is marked as containing the most recently read copy, while the remaining caches are marked as containing shared, unmodified copies of the value. When a requesting processing unit issues a message indicating that it desires to read the value, the specific cache transmits a response indicating that it cache can source the value. The response is transmitted in response to the cache snooping the message from an interconnect which is connected to the requesting processing unit. The response is detected by system logic and forwarded from the system logic to the requesting processing unit.

Abstract: An integrated circuit having electrostatic discharge protection. The integrated circuit is built from a semiconducting substrate. A circuit is formed within the semiconductor substrate. The circuit has an input and a ground. A voltage activated microelectromechanical switch is fabricated within the semiconducting substrate utilizing integrated circuit techniques. The microelectromechanical switch is coupled across the circuit input and the circuit ground. The voltage activated microelectromechanical switch couples the circuit input to the circuit ground when an electrostatic discharge voltage of sufficient magnitude is applied to the input of the circuit such that the electrostatic discharge is dissipated to ground through the microelectromechanical switch thereby protecting the circuit from ESD.