Abstract: A gate array base cell is disclosed which provides decreased input loading. The preferred base cell comprises two rows of CMOS sites. Each row comprises small CMOS sites CS and large CMOS sites CL. The transistor gates in the small CMOS site CS are narrower than the transistor gates in the large CMOS site CL. Preferably, the CS sites comprise transistor gates one half the size of transistor gates in the CL sites so that transistor gates in the CS sites may be connected in parallel to form the electrical equivalent of transistor gates in the CL sites.

Abstract: A memory cell system with properties of asymmetrical operation such that the occurrence of memory error due to certain environmental disturbances is detectable. The asymmetry of operation can be adjusted to set the level at which the disturbance is detected. Detection of memory error in the system can be used to shut off access to an associated memory array in order to prevent error in the array.