Patents Represented by Attorney Jacqueline J. Garner
  • Patent number: 8318607
    Abstract: A method of performing a single step/single solvent edge bead removal (EBR) process on a photolithography layer stack including a photoresist layer and a top coat layer using propylene glycol monomethyl ether acetate (PGMEA) or a mixture of PGMEA and gamma-butyrolactone (GBL) is disclosed. The single step/single solvent EBR process is compatible with organic and inorganic BARC layers.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: November 27, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Benjamen Michael Rathsack, Mark Howell Somervell
  • Patent number: 8309423
    Abstract: A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is preferably 100 to 10,000 times the dopant density in the cathode. The heavily doped n-type region will typically connect to an n-type buried layer under the cathode. The heavily doped n-type ring is optimally positioned at least one hole diffusion length from cathode contacts. The disclosed high voltage diode may be integrated into an integrated circuit without adding process steps.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: November 13, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer P. Pendharkar, Binghua Hu
  • Patent number: 8309957
    Abstract: An integrated circuit substrate containing an electrical probe pad structure over, and on both sides of, a dicing kerf lane. The electrical probe pad structure includes metal crack arresting strips adjacent to the dicing kerf lane. A metal density between the crack arresting strips is less than 70 percent. An electrical probe pad structure containing metal crack arresting strips, with a metal density between the crack arresting strips less than 70 percent. A process of forming an integrated circuit by forming an electrical probe pad structure over a dicing kerf lane adjacent to the integrated circuit, such that the electrical probe pad structure has metal crack arresting strips adjacent to the dicing kerf lane, and performing a dicing operation through the electrical probe pad structure.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: November 13, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Basab Chatterjee, Jeffrey Alan West, Gregory Boyd Shinn
  • Patent number: 8304317
    Abstract: A method of patterning a plurality of polysilicon structures includes forming a polysilicon layer over a semiconductor body, and patterning the polysilicon layer to form a first polysilicon structure using a first patterning process that reduces line-edge roughness (LER). The method further includes patterning the polysilicon layer to form a second polysilicon structure using a second patterning process that is different from the first patterning process after performing the first patterning process.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: November 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Yiming Gu, James Walter Blatchford
  • Patent number: 8294218
    Abstract: An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor layer with electrically active regions in which and on which the MOS device and the bipolar device are formed and electrically inactive regions for isolating the electrically active regions from each other. The MOS device comprises a gate structure and a body contacting structure, wherein the body contacting structure is formed of a base layer deposited in a selected region over an electrically active region of the semiconductor layer, and the body contacting structure is electrically connected with the gate structure. The base layer forming the body contacting structure also forms the base of the bipolar device. The present invention further relates to a method for fabricating such an integrated circuit.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: October 23, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Badih El-Kareh, Scott Gerard Balster, Hiroshi Yasuda, Manfred Schiekofer
  • Patent number: 8294210
    Abstract: A channel diode structure having a drift region and method of forming. A charge balanced channel diode structure having an electrode shield and method of forming.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: October 23, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Christopher Boguslaw Kocon, John Manning Savidge Neilson, Simon John Molloy, Haian Lin, Charles Walter Pearce, Gary Eugene Daum
  • Patent number: 8288805
    Abstract: A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral opening undercuts the gate structure.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: October 16, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Antonio Luis Pacheco Rotondaro, Tracy Q. Hurd, Elizabeth Marley Koontz
  • Patent number: 8288283
    Abstract: A process of forming an integrated circuit using a palladium CMP operation in which 25 to 125 ppm aluminum is added to the CMP slurry, allowing a palladium removal rate of at least 80 nanometers per minute at a polish pad pressure less than 9 psi and a surface speed between 1.9 and 2.2 meters per second. The palladium CMP operation may be applied to form a palladium bond pad cap after which an external bond element is formed on the palladium bond pad cap. Alternatively, the palladium CMP operation may be applied to form a palladium interconnect conductor in a first dielectric layer.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: October 16, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Mona M. Eissa, Brian E. Zinn
  • Patent number: 8288820
    Abstract: A high performance, power integrated circuit composed of two charge balanced, extended drain NMOS transistors (CBDEMOS) formed on an n-substrate. A CBDENMOS transistor with an n-type substrate source. A charge balanced channel diode (CBCD) with an n-type substrate. A process for forming a high performance, power integrated circuit composed of two CBDENMOS transistors formed on an n-substrate. A process for forming a power integrated circuit composed of one CBDENMOS transistor and one CBCD on an n-type substrate.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: October 16, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Christopher Boguslaw Kocon, John Manning Savidge Neilson, Simon John Molloy, Haian Lin, Charles Walter Pearce
  • Patent number: 8288243
    Abstract: A method of forming large microchannels in an integrated circuit by etching an enclosed trench into the substrate and later thinning the backside to expose the bottom of the trenches and to remove the material enclosed by the trench to form the large microchannels. A method of simultaneously forming large and small microchannels. A method of forming structures on the backside of the substrate around a microchannel to mate with another device.
    Type: Grant
    Filed: April 15, 2010
    Date of Patent: October 16, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Stuart McDougall Jacobsen, Byron Neville Burgess
  • Patent number: 8291354
    Abstract: Merging sub-resolution assist features includes receiving a mask pattern that includes the sub-resolution assist features. A first sub-resolution assist feature is selected to merge with a second sub-resolution assist feature. A merge bar width of a merge bar is established. A distance between the first sub-resolution assist feature and the second sub-resolution assist feature is determined. A merging technique is determined in accordance with the distance and the merge bar width. The first sub-resolution assist feature and the second sub-resolution assist feature are merged according to the identified merging technique.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: October 16, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Sean C. O'Brien, Guohong Zhang
  • Patent number: 8286929
    Abstract: A clam shell wafer holder includes a base and a lid pivotally connected with the base by an integral hinge. The base includes a rotatable wafer support, and the lid includes a universal frame and a pin holder attachment spaced inwardly from the frame. Only two contact pins are formed in a wafer-facing surface of the pin holder attachment. The contact pins are manually aligned with and contact two points on a wafer when the lid is closed against the base. A method for holding a wafer for plating is provided using the disclosed holder apparatus.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: October 16, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Kennith Ray Law, Rodney Allen Biskeborn
  • Patent number: 8278683
    Abstract: Current density in an insulated gate bipolar transistor (L-IGBT) may be increased by adding a second gate, and the corresponding MOS transistors, to the source area, which increases the base current compared to a L-IGBT with a single MOS gate. The current density may be further increased by extending the base of the bipolar transistor in the L-IGBT vertically to the bottom surface of the silicon on insulator (SOI) film in which the L-IGBT is fabricated. Adding a buffer diffused region around the sinks in the source improves the base current spatial uniformity, which improves the safe operating area (SOA) of the L-IGBT. A L-IGBT of either polarity may be formed with the inventive configurations. A method of forming the inventive L-IGBT is also disclosed.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: October 2, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Hideaki Kawahara, Philip Leland Hower
  • Patent number: 8277768
    Abstract: Systems and methods and resulting compositions of matter including silicon solids from a mixture of silicon and water. The mixture is collected at a collection stage from at least one wafer abrasion process performed on a silicon surface having an impurity concentration ?0.1 ppb and extracting one portion of the water from the mixture using at least one dryer stage to form a dry cake. The dry cake includes at least 99.99% silicon by weight excluding water and non-silicon species, where a concentration of water in the dry cake is between 0.05% and 1% by weight, and where a concentration of non-silicon species in the dry cake is between 0.05% and 1% by weight.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: October 2, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Michael Louis Hayden, Jeffrey Allen Hanson, Keith Melcher, Robert Mark Reynolds, Patricia Ann Constandine
  • Patent number: 8273645
    Abstract: A method of forming fully silicided (FUSI) gates in MOS transistors which is compatible with wet etch processes used in source/drain silicide formation is disclosed. The gate silicide formation step produces a top layer of metal rich silicide which is resistant to removal in wet etch processes. A blocking layer over active areas prevents source/drain silicide formation during gate silicide formation. Wet etches during removal of the blocking layer and source/drain metal strip do not remove the metal rich gate silicide layer. Anneal of the gate silicide to produce a FUSI gate with a desired stoichiometry is delayed until after formation of the source/drain silicide. The disclosed method is compatible with nickel and nickel-platinum silicide processes.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: September 25, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Mark Robert Visokay, Freidoon Mehrad, Richard L. Guldi, Yaw Samuel Obeng
  • Patent number: 8264055
    Abstract: A CMOS thermoelectric refrigerator made of an NMOS transistor and PMOS transistor connected in series through a cold terminal is disclosed. Active areas of the NMOS and PMOS transistors are less than 300 nanometers wide, to reduce thermal conduction between the cold terminal and the IC substrate. Drain nodes of the NMOS and PMOS transistors are connected through hot terminals to a biasing circuit. The drain node of the NMOS transistor is biased positive with respect to the drain node of the PMOS transistor, to extract hot electrons and hot holes from the cold terminal. Biases on the drain nodes and gates of the NMOS and PMOS transistors may be adjusted to optimize the efficiency of the CMOS thermoelectric refrigerator or maximize the thermal power of the CMOS thermoelectric refrigerator. The cold terminal may be configured to cool a selected component in the IC, such as a transistor.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: September 11, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Henry Litzmann Edwards
  • Patent number: 8263306
    Abstract: The present invention provides a blended solvent for solubilizing an ultraviolet photoresist. The blended solvent comprises a mixture of from about 5 vol % to about 95 vol % of a first solvent, wherein the first solvent comprises a cyclic ester. A balance of the mixture comprises a second solvent, wherein the second solvent comprises a volatile organic liquid.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: September 11, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Mark H. Somervell, Benjamen M. Rathsack, David C. Hall
  • Patent number: 8264038
    Abstract: A buried layer architecture which includes a floating buried layer structure adjacent to a high voltage buried layer connected to a deep well of the same conductivity type for components in an IC is disclosed. The floating buried layer structure surrounds the high voltage buried layer and extends a depletion region of the buried layer to reduce a peak electric field at lateral edges of the buried layer. When the size and spacing of the floating buried layer structure are optimized, the well connected to the buried layer may be biased to 100 volts without breakdown. Adding a second floating buried layer structure surrounding the first floating buried layer structure allows operation of the buried layer up to 140 volts. The buried layer architecture with the floating buried layer structure may be incorporated into a DEPMOS transistor, an LDMOS transistor, a buried collector npn bipolar transistor and an isolated CMOS circuit.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: September 11, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer P. Pendharkar, Binghua Hu, Xinfen Chen
  • Patent number: 8258041
    Abstract: A method of fabricating metal-bearing structures in an integrated circuit such as metal-polysilicon capacitors using conductive metal compounds. Defects due to organometallic polymers formed during the etch of a hard mask material are minimized by using a process that includes a plasma etch for the hard mask that achieves a predominantly chemical character using a fluorine-based etch chemistry. Using a low-temperature liquid-phase strip of the hard mask photoresist instead of an ash prevents further cross-linking of polymers formed during the plasma etch. Etching the metal-bearing material using a hot fully-concentrated mixture of ammonium hydroxide and hydrogen peroxide allows short etch times that are particularly shortened for tantalum nitride films deposited with a nitrogen concentration of about 30 percent or greater.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: September 4, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Srinivas Raghavan, Kalyan Cherukuri, Thomas E. Lillibridge, Richard A. Faust
  • Patent number: 8253205
    Abstract: An integrated circuit (IC) includes a plurality of compressively strained PMOS transistors. The IC includes a substrate having a semiconductor surface. A gate stack is formed in or on the semiconductor surface and includes a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor surface below the gate dielectric. A source and a drain region is opposing sides of the gate stack. At least one compressive strain inducing region including at least one specie selected from Ge, Sn and Pb is located in at least a portion of the source and drain regions of the PMOS transistors, wherein the strain inducing region provides ?1010 dislocation lines/cm2 and an active concentration of the compressive strain inducing specie that is above a solid solubility limit for the compressive strain inducing specie in the compressive strain inducing region.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: August 28, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Amitabh Jain