Patents Represented by Attorney Jainq Chyun IP Office
  • Patent number: 7071569
    Abstract: An electrical package and manufacturing method thereof is provided. A high stiffness, high electrical conductivity, low coefficient of thermal expansion and high thermal conductivity support substrate is used as an initial layer for building the package. A multilayer interconnection structure is formed over the support substrate. Thereafter, a plurality of openings is formed over the support substrate. The openings expose a plurality of bonding pads on a bottom surface of the multi-layer interconnection structure. An electronic device is set up over the multi-layer interconnection structure. Contacts are formed inside the opening over the bonding pads.
    Type: Grant
    Filed: June 9, 2004
    Date of Patent: July 4, 2006
    Assignee: VIA Technologies, Inc.
    Inventors: Kwun-Yao Ho, Moriss Kung