Patents Represented by Attorney James A. Sheridan
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Patent number: 6702465Abstract: A method and apparatus for a conical bearing is provided having a seal shield having an angle supported from the hub or sleeve which surrounds the shaft, and extending at an angle toward the outer surface of the shaft and spaced slightly away from the upper angular surface of the cone. As the cone and seal shield rotate relative to one another, fluid is drawn toward the lower inner region of the reservoir. However, due to shock or the like, some fluid may reach the radial gap between the end of the shield and the outer surface of the shaft, therefore, a ring is either incorporated into the upper end of the cone or pressed against the axial outer end of the cone, defining an axial gap which is smaller than the radial gap. In a preferred form of the invention, the ratio is about 1:3.Type: GrantFiled: December 13, 2001Date of Patent: March 9, 2004Inventors: Alan Lyndon Grantz, Robert Alan Nottingham, Jeffry Arnold LeBlanc, Troy Michael Herndon, Norbert Steve Parsoneault, Saul Ceballos, Hans Leuthold, Alexander Gredinberg
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Patent number: 6693754Abstract: Aspects of the invention include a method and apparatus to optimize the location of data on a disc drive storage system by optimizing the physical location of the file to allow the read ahead memory cache to operate more efficiently. In one aspect, the disc drive uses a reserved area on the media to hold files during the optimization process. In another aspect, the drive includes an optimization table that stores optimized file access data to further enhance the drive performance.Type: GrantFiled: May 24, 2001Date of Patent: February 17, 2004Assignee: Seagate Technology LLCInventors: Gayle L. Noble, Rick S. Shimizu, Jason P. Hanlon
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Patent number: 6129298Abstract: A construction vehicle attachment in the form of a pulverizer-ripper unit that includes a pair of jaws confronting and closing on one another and an independent ripper-shank that has a replaceable ripper-tooth. Each jaw includes teeth that serve to engage and fracture concrete slabs. The pulverizer-ripper unit operates under power of any one or a combination of hydraulic, pneumatic, electric, or mechanical powers. The teeth on each jaw are alternated at differing lengths and sizes. The ripper-shank is an elongated finger-like projection pivotably mounted on one of the jaws. The ripper-shank is significantly longer than either jaw and has a range of arcuate motion from a parked-position to a fully-deployed-position with at least two intermediate positions therebetween. The ripper-shank can be locked into such an intermediate position and allows an operator to initially rip up or pry up surfaces, sort and properly orient large chunks, and then subsequently pulverize the chunks with the jaws.Type: GrantFiled: March 17, 1999Date of Patent: October 10, 2000Assignee: National Attachments, Inc.Inventor: Mark Nye
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Patent number: 6129417Abstract: A shopping cart clean seat for use as a seat cover. The shopping cart clean seat made of a thin sheet of flexible material having a front sleeve and a back sleeve to secure the seat cover to the child seating area of the shopping cart. Front and back portions connect the front and back sleeves to a central bottom portion, side portions extend from the central bottom portion, and the portions together cover the child seating area of the shopping cart, respectively. The shopping cart clean seat has piping at the seams of the portions to retain its shape. The front portion of the clean seat has openings for the child's legs to pass through. The back portion of clean seat has grommet openings for a belt to pass through to retain the child.Type: GrantFiled: June 8, 1999Date of Patent: October 10, 2000Assignee: Melissa Cohen-FyffeInventor: Melissa Cohen-Fyffe
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Patent number: 4366555Abstract: An Electrically Erasable Programmable Read-Only Memory (EEPROM) requires only a single voltage applied to a single control gate for both erasing and writing operations. Writing is accomplished by hot channel electron injection to charge the floating gate of a selected device with electrons. Nonselected devices are kept from charging by either floating their sources or grounding their gates. Devices are erased by grounding the source and drain regions and causing the electrons stored in the floating gates to tunnel to the control gate. Preferred ratioing of the intra-device capacitances prevents erasure of nonselected devices during writing.Type: GrantFiled: August 1, 1980Date of Patent: December 28, 1982Assignee: National Semiconductor CorporationInventor: Chenming Hu
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Patent number: 4364977Abstract: An automatic self-adjusting processing apparatus for plating an object is described. The apparatus has a plating head, an apparatus coupled to the plating head which is responsive to the presence of the object for indicating the relative position of the plating head and the object, and an apparatus coupled to the indicating apparatus for automatically adjusting, if necessary, the relative position of the plating head and the object to a predetermined relative position.Type: GrantFiled: July 6, 1981Date of Patent: December 21, 1982Assignee: National Semiconductor CorporationInventor: Carl E. Bernardi
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Patent number: 4359693Abstract: A current comparator is supplied with differential currents based upon an amplitude modulated radio frequency carrier. The comparator outputs are summed in a combining stage the output of which will contain a direct current proportional to the average carrier level and a current variation which represents the carrier modulation. The circuit provides very efficient detection of the modulated carrier.Type: GrantFiled: September 15, 1980Date of Patent: November 16, 1982Assignee: National Semiconductor CorporationInventor: Don R. Sauer
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Patent number: 4355455Abstract: A floating gate memory cell has its control gate self-aligned to the floating gate in the source to drain direction and its floating gate self-aligned to the channel region in that direction and the direction transverse thereto without overlaying the field oxide.Type: GrantFiled: November 17, 1980Date of Patent: October 26, 1982Assignee: National Semiconductor CorporationInventor: Charles E. Boettcher
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Patent number: 4355463Abstract: A tape assembly process attaches semiconductor chips to a tape via thermocompression gang bonding and the tape is wound onto a reel. The tape is fabricated during its manufacture to have a plurality of spaced finger array patterns. The inner finger ends are located so as to mate with the bonding pads of a semiconductor device and are bonded thereto. A ring-shaped strip is included in each finger pattern that joins all of the fingers in each pattern into a unitary structure in which the fingers are accurately spaced. Where the ring joins onto the fingers, weakened regions are introduced and the side of the tape that contains the semiconductor device includes a recess that is in registry with the ring. A ceramic substrate that will ultimately mount the semiconductor device is provided with an array of conductor patterns that match the tape finger patterns. A layer of sealing glass is screened over the ceramic, so as to align with the ring.Type: GrantFiled: March 24, 1980Date of Patent: October 26, 1982Assignee: National Semiconductor CorporationInventor: Carmen D. Burns
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Patent number: 4355719Abstract: A mechanical shock and impact resistant ceramic semiconductor package is formed by applying a resilient, non-conductive, non-absorbent, heat-resistant material onto the surfaces of said package. In a dual in-line ceramic package a silicone polymer is discretely applied onto at least one end of the longitudinally opposite end edge surfaces. This renders the package mechanical shock and impact resistant.Type: GrantFiled: August 18, 1980Date of Patent: October 26, 1982Assignee: National Semiconductor CorporationInventors: Sally K. Hinds, Peter M. Weiler, Robert R. Hewitt
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Patent number: 4354162Abstract: A unity gain amplifier circuit has a control characteristic which permits a variation of the high frequency roll off as a function of a control voltage. Means are provided to prevent a change of output voltage resulting from the control voltage variation.Type: GrantFiled: February 9, 1981Date of Patent: October 12, 1982Assignee: National Semiconductor CorporationInventor: John W. Wright
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Patent number: 4353105Abstract: A protection circuit for bulk-silicon CMOS circuits detects the latch-up of parasitic SCR devices, current starves the CMOS circuit in response to detecting a SCR latch-up condition and reenables normal circuit operation once the latch-up condition has been terminated.Type: GrantFiled: December 8, 1980Date of Patent: October 5, 1982Assignee: National Semiconductor CorporationInventor: William C. Black
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Patent number: 4348602Abstract: A pair of differentially related currents are caused to flow in a pair of current modes. A symmetrical current mirror is coupled to the nodes and level shifting means coupled from each node to the current mirror common terminal. A pair of output transistors have their bases directly coupled to the nodes and their emitters cross coupled to the same nodes so that when the nodes are driven to a one V.sub.BE differential, output collector current will flow. The output transistors have their collectors commonly coupled to the circuit output. Deadband control means are connected to the current mirror common terminal so that no output current will flow until the deadband differential is exceeded.Type: GrantFiled: September 15, 1980Date of Patent: September 7, 1982Assignee: National Semiconductor CorporationInventor: Don R. Sauer
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Patent number: 4347654Abstract: A method of fabricating a high-frequency bipolar transistor structure wherein the emitter, higher impurity concentration base, and lower impurity concentration base regions are defined in a single masking operation. Permeation etching is used to etch regions of an oxide layer under a layer of resist which defines regions of the higher impurity concentration thereby simultaneously defining the emitter and lower impurity concentration base regions. The higher impurity concentration base regions are formed by ion implantation of impurities through the unetched oxide regions. The resist is then removed and the lower impurity concentration base and emitters are formed through the resulting opening in the oxide. This results in the self-aligning of the emitter regions with respect to the base regions.Type: GrantFiled: June 18, 1980Date of Patent: September 7, 1982Assignee: National Semiconductor CorporationInventors: Bert L. Allen, Robert L. Wourms, Daniel C. Hu
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Patent number: 4346454Abstract: A bubble memory chip includes a plurality of data loops, some of which may be defective, for storing magnetic bubbles representative of data therein. A serial-parallel input propagation path and a parallel-serial output propagation path are provided for propagating bubbles to and from the data loops. A plurality of spaced apart permalloy disk elements are provided, each adapted for having a single bubble circulated thereabout in the presence of an in-plane rotating magnetic drive field. A stream of bubbles representative of an error map indicating which of the data loops are defective is loaded onto and read from the disk elements to initialize the memory. A plurality of gates permit the bubbles of the error map to be transferred between an error map propagation path and the disk elements in parallel fashion upon pulsing of an adjacent control conductor. The potential for data scrambling in the error map is eliminated.Type: GrantFiled: August 22, 1980Date of Patent: August 24, 1982Assignee: National Semiconductor CorporationInventor: Peter K. George
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Patent number: 4346351Abstract: A differential oscillator is supplied with a constant total current. A signal-controlled single-ended shunt circuit bypasses current around the oscillator thus varying the tail current oppositely. This in turn varies the signal delay in the oscillator transistors and hence oscillator frequency.Type: GrantFiled: February 28, 1980Date of Patent: August 24, 1982Assignee: National Semiconductor CorporationInventor: Milton E. Wilcox
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Patent number: 4345218Abstract: In an amplifier circuit the output devices are thermally coupled to a shutdown circuit. A first latch is designed to operate at a first high temperature excursion. The first latch operation acts to shut the output devices off and to invoke a second latch. The second latch operates between a low temperature and a second high temperature that is below the first high temperature. Thus, after the first latch operates, the second latch will operate to cycle between a low temperature whereupon it energizes the output devices and a high temperature at which it deenergizes the output devices. By this action, the circuit will permit only one high temperature peak after which it will cycle between a lower high temperature peak and a low temperature. This avoids repeated cycling to a high temperature that could be deleterious to the circuit devices or the package in which they are housed.Type: GrantFiled: September 8, 1980Date of Patent: August 17, 1982Assignee: National Semiconductor CorporationInventors: James S. Congdon, Tim D. Isbell
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Patent number: 4339728Abstract: An integrated circuit is employed to provide a high gain signal amplifier having an automatic gain control function and an output suitable for driving signal detection circuitry in a radio receiver. The circuit operates at the receiver intermediate frequency. A gain controlled cascode amplifier drives one input of a high gain differential amplifier. The other input is returned to a reference potential. A pair of current mirrors are coupled into the differential amplifier to provide a pair of single ended outputs. One output drives a peak rectifying diode to operate the automatic gain control and the other output drives a signal detection circuit. The current mirrors are ratioed so that the automatic gain control threshold is a predetermined fixed multiple of the signal threshold.Type: GrantFiled: February 11, 1980Date of Patent: July 13, 1982Assignee: National Semiconductor CorporationInventor: Dennis M. Monticelli
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Patent number: 4338590Abstract: A multi-stage resistive ladder network which uses extra stages to trim out resistance discrepencies. All of the stages are interconnected in a series. Nominally, current is divided in half within each stage. Half of the current is gated onto a bus in response to logic control signals, and the other half of the current is passed onto the next succeeding stage. Due to various processing limitations, the resistors comprising each stage vary slightly from their nominal value, which in turn upsets the current division. To compensate for this additional current dividing stages are serially connected to the last stage of the ladder. Current from these additional stages are selectively coupled onto the bus in response to the logic signals in addition to the current which is normally coupled thereto.Type: GrantFiled: January 7, 1980Date of Patent: July 6, 1982Assignee: National Semiconductor CorporationInventors: Joseph J. Connolly, Jr., James B. Cecil
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Patent number: D433169Type: GrantFiled: October 19, 1999Date of Patent: October 31, 2000Inventor: Theodore W. Sullivan