Abstract: A circuit and method biases signal pins, such as the output enable pin and other input pins, of an integrated circuit to a predetermined level during power-up of the integrated circuit. The circuit can be incorporated into the chip-level design of the integrated circuit, such as a CMOS device. The circuit has a pull-up/pull-down biasing section, a sensing section, and a latch section to bias the output enable signal to a disabled or inactive level during power-up. A bus hold section can additionally be provided to bias the other input pins of the integrated circuit to a fixed, solid logic level during power up. When an external output enable input is applied to activate the output enable pin, the circuit releases the bias applied to the output enable pins and the other input pins.

Abstract: This is a method and system of communicating on a data and computer communications network.

Abstract: A hybrid focal plane array has p-n junction photodiodes formed in a substrate (10) of HgCdTe which is passivated by a cap layer (12) of Cd-rich CdTe. The active surface of the HgCdTe substrate is passivated by annealing at a temperature sufficient to support interdiffusion between the Cd-rich CdTe capping layer (12) and the HgCdTe substrate (10). Use of the CdTe capping layer (12) with a slight excess Cd maintains the surface of the HgCdTe substrate (10) in a metal-rich phase condition.

Abstract: An npn transistor having a low collector-base breakdown voltage. An emitter region (104, 106) of a first conductivity type is located in a semiconductor substrate (102). A base region (14) of a second conductivity type is located within the emitter region (104,106) and a shallow collector region (18) of the first conductivity type is located within the base region (14). The shallow collector region (18) may be doped with arsenic and/or phosphorus such that the dopant concentration and depth of the shallow collector region (18) provide a low collector-base breakdown voltage.

Abstract: Thermal isolation mesas 36 comprising a porous material 64 are used to thermally insulate sensing integrated circuitry 44 from pixels 34 of an uncooled IR detector hybrid system 30. The porous material 64 is preferably a silicon-dioxide xerogel. The mesas 36 may also comprise a protective film 66.

Abstract: A method for manufacturing semiconductor device having metal leads 14 with improved reliability, and device for same, comprising metal leads 14 on a substrate 12, a low-dielectric constant material 18 at least between the metal leads 14, and thermoconductive insulating layer 22 deposited on the metal leads 14 and the low-dielectric constant material 18, and dummy leads 16 proximate metal leads 14. Heat from the metal leads 14 is transferable to the dummy leads 16 and thermoconductive insulating layer 22, which are both capable of dissipating the heat. A thin thermoconductive layer 24 may be deposited over the metal leads 14 prior to depositing at least the low-dielectric constant material 18 and the thermoconductive insulating layer 22. The low-dielectric constant material 18 has a dielectric constant of less than 3.5. An advantage of the invention is to improve reliability of metal leads for circuits using low-dielectric constant materials.

Abstract: A method for forming air gaps 22 between metal leads 16 of a semiconductor device and semiconductor device for same. A metal layer is deposited on a substrate 12. The metal layer is etched to form metal leads 16. A disposable solid layer 18 is deposited between the metal leads 16. A porous dielectric layer 20 is deposited on the disposable solid layer 18 and the tops of the leads 16, and the disposable solid layer 18 is removed through the porous dielectric layer 20, to form air gaps 22 between the metal leads 16 beneath the porous dielectric layer 20. The air gaps have a low-dielectric constant and result in reduced sidewall capacitance of the metal leads.