Abstract: A layer of dopant is implanted in the passivation of a semiconductor die to facilitate testing of the die by a scanning electron microscope voltage contrast system. The layer of dopant is capacitively coupled to circuits under the passivation and is coupled to ground to allow charge to bleed to ground through a high resistivity path. The resistivity is low enough to allow E-beam charge bleed off, but not bleed off of higher frequency capacitive coupled signals. The disclosure is also applicable to photo generated electron voltage contrast.
Type:
Grant
Filed:
December 6, 1993
Date of Patent:
April 11, 1995
Assignee:
Texas Instruments Incorporated
Inventors:
Kendall S. Wills, John S. Bartlett, Thomas J. Aton, David E. Littlefield