Patents Represented by Attorney, Agent or Law Firm James C. Pintner
  • Patent number: 5542073
    Abstract: A method for choosing join selectivities in a query optimizer in a relational database management system is disclosed which facilitates the estimation of join result sizes by a query optimizer in a relational database system, wherein a new relation R is to be joined with an intermediate relation I, and wherein the selectivity values for each eligible join predicate are known. The method has the steps of determining the equivalence classes for a plurality of join attributes and then computing for each relation an estimate of the cardinality and the number of distinct values in each attribute after all the local predicates have been included. These are used in further computation of join selectivities and join result sizes. The join predicates must then be processed by correctly choosing the join selectivities. The join result sizes can then be correctly calculated.
    Type: Grant
    Filed: August 1, 1995
    Date of Patent: July 30, 1996
    Assignee: International Business Machines Corporation
    Inventors: Klaus B. Schiefer, Arun N. Swami
  • Patent number: 5539826
    Abstract: A method is provided for authentication of encrypted messages. A non-malleable public-key encryption technique is employed, so that an eavesdropper cannot employ an encrypted message, previously overheard, to generate a message which, when sent to a recipient, which would pass as a message originating from a valid sender. In a preferred embodiment, a protocol is provided in which, in response to a message authentication request from a sender, a recipient sends the sender a string, encrypted according to the sender's non-malleable public key. The sender decrypts the string using its private key, and sends the recipient a message which is a function of the string and the message to be authenticated. Because of the non-malleability of the public keys, an eavesdropper cannot impersonate the sender or the recipient and produce a disinformation message which would nevertheless contain the correct authorization string.
    Type: Grant
    Filed: December 29, 1993
    Date of Patent: July 23, 1996
    Assignee: International Business Machines Corporation
    Inventors: Cynthia Dwork, Simeon Naor
  • Patent number: 5539883
    Abstract: A method is described of operating a computer in a network of computers using an improved load balancing technique. Logical links are generated between the computer and other computers in the network so that a tree structure is formed, the computer being logically linked to one computer higher up the tree and a number of computers lower down the tree. Stored information is maintained in the computer regarding the current load on the computer and the load on at least some of the other computers in the network by causing the computer periodically to distribute the information to the computers to which it is logically linked, and to receive from the computers similar such information and to update its own information in accordance therewith, so that the information can be used to determine a computer in the network that can accept extra load.
    Type: Grant
    Filed: April 20, 1994
    Date of Patent: July 23, 1996
    Assignee: International Business Machines Corporation
    Inventors: David Allon, Moshe Bach, Yosef Moatti, Abraham Teperman
  • Patent number: 5535217
    Abstract: A probabilistic dock synchronization scheme for synchronization of time docks between nodes on a communication network is disclosed, in which a round trip exchange of messages is used to establish that one time according to a first time scale falls between two times according to a second time scale. A time related to the two second time scale times, preferably midway between the two times, is used for synchronizing with the time according to the first time scale. Each time is given in terms of a time value and a plus-or-minus precision range, thereby defining an interval. Enhanced precision is achieved by computing a new precision range for the synchronized time based on an intersection between the intervals of the related time and the time according to the first time scale.
    Type: Grant
    Filed: December 20, 1994
    Date of Patent: July 9, 1996
    Assignee: International Business Machines Corporation
    Inventors: Yiu M. Cheung, Kenneth K. W. Ng, Hovey R. Strong, Jr.
  • Patent number: 5522019
    Abstract: Methods and apparatus are provided for generating isosurfaces, given input data that includes (1) the representation of a set of points in three-dimensional space; (2) connectivity information with respect to the set of points and (3) a scalar field. The methods and apparatus allow the desired isosurfaces to be produced efficiently on all hardware platforms, including those not equipped to rapidly generate such isosurfaces using normally computation intensive processes, by utilizing a precomputed isofacet configuration table and predefined tetrahedron component labeling data (preset relationships among the vertices, edges and faces of a tetrahedron). Further aspects of the methods and apparatus include (1) methods and apparatus which support the selective display of isosurface and contour line images, and (2) methods and apparatus which utilize parallel processing techniques to enhance the efficiency of the isosurface generation process.
    Type: Grant
    Filed: July 14, 1995
    Date of Patent: May 28, 1996
    Assignee: International Business Machines Corporation
    Inventors: Gregory P. Bala, Koji Koyamada
  • Patent number: 5513371
    Abstract: Two new classes of interconnection networks are described. The new classes of interconnection networks are referred to herein as the hierarchical shuffle-exchange (HSE) and hierarchical de Bruijn (HdB) networks. The new HSE and HdB networks are highly regular and scalable and are thus well suited to VSLI implementation. In addition, they can be adjusted to match any set of packaging constraints. These new networks are also efficient in supporting the execution of a wide range of algorithms on computers whose processors are interconnected via one of the networks fabricated in accordance with the teachings of the invention. Such computers, also contemplated by the invention, are referred to herein as HSE and HbB computers. Furthermore, methods for implementing the aforementioned wide range of algorithms, particularly those in the classes of Ascend and Descend algorithms, on the novel HSE and HdB computers, constitute a further aspect of the invention.
    Type: Grant
    Filed: January 24, 1995
    Date of Patent: April 30, 1996
    Assignee: International Business Machines Corporation
    Inventors: Robert E. Cypher, Jorge L. C. Sanz
  • Patent number: 5513354
    Abstract: A method and apparatus are disclosed for managing tasks in a network of processors. After a period of time has elapsed, during which the processors of the network have been executing tasks allocated to them, the processors exchange views as to which pending tasks have or have not been completed. The processors reach a consensus as to the overall state of completion of the pending tasks. In a preferred embodiment, the processors exchange views and update their views based on the views received from the other processors. A predetermined condition determines that a consensus has been reached. The predetermined condition is preferably two sets of exchanges in which a processor has received messages from the same set of other processors. Alternatively, the condition is an exchange which does not result in any updates to a processor's view.
    Type: Grant
    Filed: December 18, 1992
    Date of Patent: April 30, 1996
    Assignee: International Business Machines Corporation
    Inventors: Cynthia Dwork, Joseph Y. Halpern, Hovey R. Strong, Jr.
  • Patent number: 5513313
    Abstract: A method is disclosed, for use with a multiprocessing hardware mesh architecture including nodes and a network of interconnections between the nodes, for defining and implementing a target logical mesh architecture utilizing a given subset of the nodes and the interconnections of the hardware architecture. Typically, the hardware mesh architecture includes redundant nodes and interconnections, sot hat the target logical mesh architecture may be defined from the hardware architecture several different ways. As a consequence, the target logical mesh architecture may be defined even in the presence of faulty nodes or interconnections in the hardware architecture. Frequently, the logical mesh is defined in terms of some regular pattern of interconnections.
    Type: Grant
    Filed: August 31, 1995
    Date of Patent: April 30, 1996
    Assignee: International Business Machines Corporation
    Inventors: Jehoshua Bruck, Robert E. Cypher, Ching-Tien Ho
  • Patent number: 5510912
    Abstract: A modulator apparatus for modulating arrays of input data V.sub.in to be stored in a holographic recording medium is disclosed wherein the final output data array V.sub.out has frequent transitions from light to dark and from dark to light in either dimension across the data page and has the total amount of illuminated regions throughout the entire data page held constant. These two constraints are achieved by a first set of control arrays obtained from two fixed sets of m.times.n binary arrays {A.sub.0, A.sub.1, . . . , A.sub.n } and {B.sub.0, B.sub.1, . . . , B.sub.m } which in turn are obtained from fixed sets of binary control vectors {a.sub.0, a.sub.0, a.sub.1, . . . , a.sub.n }, {b.sub.0, b.sub.1, . . . , b.sub.m }, respectively. The control vectors a.sub.0, a.sub.1, . . . , a.sub.n any n+1 fixed elements of the inverse mapping, .phi. .sup.1 (C.sub.1), of the (t-2) error-correcting code C.sub.1 of length m. The control vectors b.sub.0, b.sub.1, . . . , b.sub.
    Type: Grant
    Filed: August 9, 1993
    Date of Patent: April 23, 1996
    Assignee: International Business Machines Corporation
    Inventors: Miguel M. Blaum, Paul H. Siegel, Glenn T. Sincerbox, Alexander Vardy
  • Patent number: 5495601
    Abstract: A method is disclosed for a database system for [off-loading] off-loading, to disk [controller] controller, the extraction of committed [data involving the] data. The system first [picking] picks a Commit.sub.-- LSN value and [insuring] insures all the data modified prior to the Commit.sub.-- LSN value is processed following the DBMS policy of reducing some disk I/Os or not for the modified pages cached in the system. If the policy is not to do disk I/Os for such [pages] pages, then the system places the identifiers of those pages in an ignore list. Otherwise, the system writes those pages to disk and empties the ignore list. [After which] Afterwards, the system forwards the ignore list and the Commit.sub.--LSN along with information regarding the data to be processed to the controller. The controller performs the off-load function by reading from disk every page identified by the system except those in the ignore [list] list, and [determining] determining, for each [page] page, if the page's Page.sub.
    Type: Grant
    Filed: December 11, 1992
    Date of Patent: February 27, 1996
    Assignee: International Business Machines Corporation
    Inventors: Inderpal S. Narang, Balakrishna R. Iyer, Chandrasekaran Mohan
  • Patent number: 5488727
    Abstract: Methods and related apparatus, for use in programming language systems, are set forth which support compile-time type checking for overloaded functions in an environment supporting subtypes with multiple inheritance. At both compile and runtime, the invention considers the type of all actual arguments of a function to select a proper function instance to execute. Furthermore, the methods contemplated by the invention identify at compile time the set of function instances which might be invoked due to subtype substitutions for the actual arguments. Since type errors on function invocations or variable assignments are usually indicative of a programming error, program reliability can be improved and faults that would otherwise result in runtime errors can be corrected through the use of the invention prior to program deployment.
    Type: Grant
    Filed: September 30, 1991
    Date of Patent: January 30, 1996
    Assignee: International Business Machines Corporation
    Inventors: Rakesh Agrawal, Linda G. De Michiel, Bruce G. Lindsay
  • Patent number: 5469568
    Abstract: A method for choosing join selectivities in a query optimizer in a relational database management system is disclosed which facilitates the estimation of join result sizes by a query optimizer in a relational database system, wherein a new relation R is to be joined with an intermediate relation I, and wherein the selectivity values for each eligible join predicate are known. The method has the steps of determining the equivalence classes for a plurality of join attributes and then computing for each relation an estimate of the cardinality and the number of distinct values in each attribute after all the local predicates have been included. These are used in further computation of join selectivities and join result sizes. The join predicates must then be processed by correctly choosing the join selectivities. The join result sizes can then be correctly calculated.
    Type: Grant
    Filed: January 7, 1993
    Date of Patent: November 21, 1995
    Assignee: International Business Machines Corporation
    Inventors: Klaus B. Schiefer, Arun N. Swami
  • Patent number: 5461631
    Abstract: A method is disclosed for recovery from synchronization errors caused by deletions and/or insertions of symbols in the presence of errors that alter the symbols in any code constrained binary record. The method initially divides the sequence of data into equal size blocks before appending a binary sync sequence at the end of each block not encountered in the block. Then, the blocks are resynchronized by first determining the size of any symbol insertions and/or deletions that have occurred. Then, scanning for the sync sequence starting at the presumed end of the data field of the current block so as to determine the offset of the sync sequence with respect to that specific location. After this location of the insertions and/or deletions has been determined, a corresponding number of symbols can be added or deleted from the middle of the block according to the offset determined by the present method.
    Type: Grant
    Filed: December 15, 1992
    Date of Patent: October 24, 1995
    Assignee: International Business Machines Corporation
    Inventors: Miguel M. Blaum, Jehoshua Bruck, Constantin M. Melas
  • Patent number: 5450443
    Abstract: An encoding apparatus for constructing an asymptotically optimal coding scheme for second order DC-constrained channels is disclosed. A first encoding function block breaks an input data stream into equal sized vectors of length m bits. A sign designation bit is then attached to each vector to make vectors of length m+1 bits. r redundancy bits are added to each vector, to produce balanced vectors of length m+1+r bits. A first moment is calculated for each vector. A determination is made whether the addition of this vector's first moment value to an accumulated running sum of all the vectors' first moments effectively drives the running sum in the direction of zero. If is does then that vector's first moment is added to the accumulated running sum of first moments and the vector is added to the output array.
    Type: Grant
    Filed: September 1, 1993
    Date of Patent: September 12, 1995
    Assignee: International Business Machines Corporation
    Inventors: Paul H. Siegel, Alexander Vardy
  • Patent number: 5444701
    Abstract: A method is for routing packets in parallel computers with torus interconnection networks of arbitrary size and dimension having a plurality of nodes, each of which contains at least 2 buffers per edge incident to the node. For each packet which is being routed or which is being injected into the communication network, a waiting set is specified which consists of those buffers to which the packet can be transferred. The packet can be transferred to any buffer in its waiting set which has enough storage available to hold the packet. This waiting set is specified by first defining a set of nodes to which the packet is allowed to move and then defining a candidate set of buffers within the defined set of nodes. Then, defining an ordering of the nodes across the network from smallest to largest. The buffers in each node are then classified into four classes.
    Type: Grant
    Filed: October 29, 1992
    Date of Patent: August 22, 1995
    Assignee: International Business Machines Corporation
    Inventors: Robert E. Cypher, Luis Gravano
  • Patent number: 5379000
    Abstract: An atomic clock system employs one of a family of ion trap configurations confining an ion in a potential well, such that a vibrational frequency confined ion may be measured accurately. The ion traps disclassed for use in such atomic clock systems include configurations of ring-shaped conductive members, or sheets of conductive material having circular holes therein. The trap apparatus further has a means to apply an RF field such that the resulting electric field being generated in a space defined by the conductive members has a characteristic of a substantially quadrupole field whereby a charged particle, being injected into the space, is confined in said field, maintaining a dynamic equilibrium condition.
    Type: Grant
    Filed: October 30, 1992
    Date of Patent: January 3, 1995
    Assignee: International Business Machines Corporation
    Inventors: Richard G. Brewer, Ralph G. Devoe, Kenneth L. Foster, John A. Hoffnagle, Reinald Kallenbach
  • Patent number: 5357250
    Abstract: A method and apparatus are provided for adaptively and predictively determining probabilities of occurrence for each symbol of a finite alphabet within a symbol string. A plurality of intervals are defined over a portion of the symbol string. As successive new symbols are added to the string, they enter the intervals, and old symbols pass out of the intervals. A probability for each symbol of the alphabet is maintained and updated by the following process. For each new symbol which enters the intervals, it is determined whether the new symbol is a given character of the alphabet, and whether each old symbol leaving each interval is the given character. Accordingly, the number of occurrences of the given character within each interval may change. A probability update value is determined, having a component from each interval determined by whether the number of occurrences of the given character in that interval changed.
    Type: Grant
    Filed: November 20, 1992
    Date of Patent: October 18, 1994
    Assignee: International Business Machines Corporation
    Inventors: Paul D. Healey, Jorma J. Rissanen
  • Patent number: 5319779
    Abstract: This invention encodes information (such as the field values of a database record, or the words of a text document) so that the original information may be efficiently searched by a computer. An information object is encoded into a small "signature" or codeword using a method. A base or "leaf" signature S1 34 is computed by a known technique such as hashing. The logical intersection (AND) of each possible combination of pairs of bits of the base signature is computed, and the result is stored as one bit of a longer combinatorial signature CS1 42. The bit-wise logical union (bit-OR) of the combinatorial signatures of a group of records produces a second-level combinatorial signature CS2 52 representing particular field values present among those records. Higher-level combinatorial signatures CS3 60, CS4, etc. are computed similarly.
    Type: Grant
    Filed: February 19, 1992
    Date of Patent: June 7, 1994
    Assignee: International Business Machines Corporation
    Inventors: Walter W. Chang, Hans G. Schek
  • Patent number: 5271014
    Abstract: A method and apparatus are presented for tolerating up to k faults in a d-dimensional mesh architecture based on the approach of adding spare components (nodes) and extra links (edges) to a given target mesh where m spare nodes (m.gtoreq.k) are added and the maximum number of links per node (degree of the mesh) is kept small. The resulting architecture can be reconfigured, without the use of switches, as an operable target mesh in the presence of up to k faults, regardless of their distribution. According to one aspect of the invention, given a d-dimensional mesh architecture having N=n.sub.1 .times.n.sub.2 .times.. . . .times.n.sub.d nodes, the fault-tolerant mesh can be represented by a diagonal or circulant graph having N+m-k nodes, where m.gtoreq.k. This graph has the property that given any set of k or fewer faulty nodes, the remaining graph, after the performance of a pre-determined node renaming process, is guaranteed to contain as a subgraph the graph corresponding to the target mesh M so long as d.
    Type: Grant
    Filed: May 4, 1992
    Date of Patent: December 14, 1993
    Assignee: International Business Machines Corporation
    Inventors: Jehoshua Bruck, Robert E. Cypher, Ching-Tien Ho
  • Patent number: 5265244
    Abstract: A data access structure facilitates the processing of statistical queries concerning records stored in the structure. The structure, according to the present invention, includes a plurality of data nodes storing the records, and a plurality of access nodes, each storing at least one pointer to another access node or to a data node, and arranged according to an organization whereby each access node is linked directly or indirectly to at least one data node. Statistical information is stored in or linked to the nodes of a subset of the plurality of access nodes and data nodes. The statistical information concerns the records stored in the data node or data nodes linked directly or indirectly to the respective nodes of the subset. Further, a software algorithm is provided responsive to changes in the records stored in the data nodes for updating the statistical information in the access structure concerning the records stored in the data node.
    Type: Grant
    Filed: June 22, 1990
    Date of Patent: November 23, 1993
    Assignee: International Business Machines Corporation
    Inventors: Sakti P. Ghosh, Raymond A. C. Lorie