Patents Represented by Attorney, Agent or Law Firm James Cioffi
  • Patent number: 6648979
    Abstract: A semiconductor wafer is cleaned while a sponge or brush is pressed against the wafer with a constant forced applied utilizing a bias in a constant force pencil. The wafer is cleaned in the state wherein a collapsing portion of the constant force pencil with respect to the cleaning sponge cloth is set in such a way that the cleaning pressure, which is applied from the cleaning sponge to the wafer, can be constant and is adjustable. A method for cleaning wafers using a constant force pencil is also described.
    Type: Grant
    Filed: January 24, 2001
    Date of Patent: November 18, 2003
    Assignee: International Business Machines Corporation
    Inventors: Michael F. Lofaro, Marc Mattaroccia, Leonard C. Stevens, Jr.
  • Patent number: 6555912
    Abstract: A corrosion resistant electrode structure for interconnecting a decoupling capacitor to a substrate is disclosed. In an exemplary embodiment of the invention, the electrode structure includes a first chromium layer formed upon the capacitor and a first nickel layer formed upon the first chromium layer. A noble metal conductive layer is then formed upon the first nickel layer and a second nickel layer is formed upon said noble metal conductive layer. The second nickel layer has a thickness which is greater than a thickness of the first nickel layer. A second chromium layer is then formed upon the nickel layer.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: April 29, 2003
    Assignee: International Business Machines Corporation
    Inventors: Bruce A. Copeland, Rebecca Yung Gorrell, Donald W. Scheider, Mark A. Takacs, Kenneth J. Travis, Jr., Peter O. Ulanmo, Jun Wang
  • Patent number: 6552938
    Abstract: A column redundancy system is disclosed for a memory array having a page structure organized into columns and data lines. In an exemplary embodiment of the invention, the system includes a steering logic network for coupling a memory input/output (I/O) device to the memory array. A storage register is in communication with the steering logic network, the storage register for storing location information for defective data lines in the memory array. During a memory operation, the location information stored in the storage register is transmitted to the steering logic network, the storage register further having the location information loaded therein prior to the memory operation. Thereby, the steering logic network prevents any of the defective data lines from being coupled to the I/O device.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: April 22, 2003
    Assignee: International Business Machines Corporation
    Inventors: Darren L. Anand, John E. Barth, Jr.