Abstract: A random digital signal generator circuit responsive to a clock signal from a block signal source for outputting a sequential series of logic signals. The circuit comprises a clocked flip-flop that provides a signal at its output terminal that has a value corresponding to the state of its input signal until a subsequent clock signal is received. An array of oscillator signal generators is provided with each oscillator signal generator operating at a different frequency. An EXCLUSIVE-OR network means having an array of input terminals has each input terminal of the EXCLUSIVE-OR network coupled to the output terminal of a corresponding oscillator signal generator. The EXCLUSIVE-OR network provides a random output signal at its output terminal. The EXCLUSIVE-OR network means output terminal is coupled to the flip-flop input terminal. The flip-flop responds to each the clock signal to sample the state of the random output signal from the EXCLUSIVE-OR network.

Abstract: A digital image interface system converts digital image information from a first format to a second format. The interface system includes a data input line for receiving input data, which may include a plurality of frames and fields of digital image information in a first format. An image buffer memory comprising first and second buffers is connected to the input line for storing the input digital image information. Each buffer is sufficient for storing one of the fields or frames of digital image information. A data output line is connected to the buffers for outputting the digital image information from the memory. A controller includes programmable logic arrays programmed according to the first data format, the second data format, and a predetermined memory format.

Abstract: A method of fabricating multiple layer, solid, thin films on a substrate having a surface to be coated, the method providing control over the thickness, stoichiometry, and morphology of each separate layer formed by a method comprising steps: A. forming a first ion beam from an inert gas; B, bombarding a target surface with said first ion beam in a vacuum chamber to generate a vapor cloud composed of the target material atoms by the process of sputtering; C. adjusting the respective positions of the substrate surface for coating and the target surface to promote the condensation of the vapor upon the substrate surface for coating; D. forming a second ion beam, the second ion beam's ions being formed from a mixture of inert and reactive gases; E.

Abstract: An interface circuit having a first reference terminal and a first input terminal for receiving a first input current signal, referenced to said first reference terminal from a first input current signal source. The circuit also has a second reference terminal and a second input terminal for receiving a second input current signal referenced to said second reference terminal from a second input current signal source. The second input current signal has a first and second signal current level. The interface circuit comprises a first receiver means coupled between the first input terminal and a first receiver means reference terminal. The first receiver means is responsive to the first input current signal first and second signal current levels for providing a first output signal at respective first and second levels. The first output signal is referenced to the second reference potential at a first signal output terminal.

Abstract: A synthetic quadrature generating apparatus responsive to an input reference signal of the form SIN(wt) from an input reference signal source and to an error shifted quadrature signal of the form COS(wt+L) for forming a quadrature output signal of the form COS(wt)*COS(L) substantially free of error shift. The apparatus comprises an error signal synthesizing filter means responsive to the input reference signal and to the error shifted quadrature signal for forming a filtered signal of the form SIN(L); a correction means responsive to the input reference signal and to the filtered signal for forming their product as a filtered product signal; and a means responsive to the filtered product signal and the error shifted quadrature signal for forming their sum as an output quadrature signal of the form COS(wt)*COS(L).

Abstract: A range control system positioned within a stationary housing comprising: a pulse oscillator for providing a clock signal; and a transmitter receiver circuit that directionally transmits an acoustic pulse signal to a target and receives an echo from the target to provide an amplified echo signal. A timing circuit means is included for providing a range gate signal characterized to start with each clock signal and to have a predetermined duration characterized to provide a time for the acoustic pulse to travel to the target and for the echo to return from the target. An alarm signal is provided to indicate that an echo signal is being received prior to the termination of the range gate signal. A ring blanking gate signal source provides a ring blanking gate signal commencing with each clock signal and having a duration longer than the tailoff ringing of the acoustic pulse. A diode clamp is coupled to the transducer drive circuit echo signal output.

Abstract: Electronic countermeasure technique for protecting low-flying aircraft from radiant energy guided missiles by bouncing a decoy guidance signal off the ground near the aircraft.

Abstract: A universal solid state power controller for controlling the application of a source voltage to a load comprising a semiconductor switch having a predetermined non-bounce switching characteristic. The switch is responsive to an operating signal for connecting the load to the source voltage. A control means has a microcomputer following a predetermined program. The control means is responsive to a command electrical signal and provides the semiconductor switching means operating signal. The microcomputer program has an ac subprogram for SSPC operation with a source voltage of sinusoidal character and a dc subprogram for SSPC operation with a source voltage of direct current character. A voltage selection circuit provides a logic signal of a first polarity to the microcomputer to direct the microcomputer to use the ac subprogram for SSPC operation with an ac source. The logic signal has a second polarity to direct the microcomputer to use the SSPC dc subprogram for operation with a dc source.

Abstract: A hydrofoil apparatus for attachment to a marine vessel having a first pivot means for positioning the rotational axis of a gooseneck shaft parallel to the yaw axis of the hull and a trailing load support arm having a forward end coupled to the gooseneck. A planing surface sensor or planing foil rides on the water surface. The planing surface provides a hydrodynamic force to hold the planing surface sensor on surface as the vessel moves with forward velocity. An elongated body member is pivotally coupled to rotate on a first pitch axis with respect to said planing surface sensor. The elongated body member is pivotally coupled to the trailing load support at its aft end. A vertical fin is coupled to support the elongated body member. The fin maintains the planing surface sensor forward of said second pitch axis. A lifting foil raises the bow of said marine vessel by provide a lifting force via the fin.

Abstract: A dc power switch responsive to an input signal referenced to a signal reference terminal and having a power input terminal connected to a dc voltage source and a power output terminal connected to a load. The dc switch has an isolated voltage source referenced to the signal reference terminal; a current limiting resistor; and a two-pole switching circuit for coupling the isolated voltage source to the current limiting resistor. An output switching circuit couples current from the voltage source via the conduction channel to the signal reference terminal. A sense resistor has a first terminal coupled to the signal reference terminal and a second terminal coupled to the power output terminal. A SCR switching circuit latches into a conducting state in response to the firing signal and shunting current from the isolated source via the current limiting resistor second terminal to the power output terminal thereby shunting the control signal high state to a control signal low state in response to the firing.

Abstract: An isolated controller circuit responsive to an input signal voltage from the output of a low-pass filter referenced to an isolated reference potential; the controller circuit being characterized to provide a control signal at a signal output terminal referenced to a non-isolated reference potential. The isolated controller circuit comprises: a reference signal source referenced to the isolated reference potential for providing a reference signal and an amplifier and compensation means for amplifying and compensating the signal difference between the input signal and the reference signal to provide a compensated control signal referenced to the isolated reference potential. The controller circuit also has an oscillator and coupling means for coupling and scaling the compensated control signal referenced to the isolated reference potential and it provides the control signal at the signal output terminal referened to the non-isolated reference potential.

Abstract: A non-volatile memory cell circuit for storing and recalling a digital signal, the memory cell circuit having a store cycle having a repeating series of recurring store cycle sequences; each store cycle sequence being controlled by an HIV Signal and a STORE SIGNAL. The memory cell circuit also has a recall cycle controlled by a MEMORY RESET SIGNAL to preset the state of the memory cell circuit during a first interval, a RECALL OUTPUT CONTROL SIGNAL and a RECALL TRANSFER SIGNAL in a second reset signal interval. The memory cell has a VOLATILE RAM CELL with a flip-flop having first and second nodes at which complementary output signals are provided. The flip-flop also has a SET TERMINAL responsive to a set signal for forcing the flip-flop to assume a predetermined state coupled to the first node and a RESET TERMINAL responsive to the RESET SIGNAL.

Abstract: A solid state dc switch for switching power from the positive terminal of a ground referenced dc voltage source to the terminal of a ground referenced load. The solid state switch has a divide-by-two circuit means responsive to a clock signal and to a control signal first state for providing first and second symmetrical output signals at a frequency of one-half the frequency of said clock frequency. It also has a transformer drive and rectifier means for providing an isolated dc signal. An isolated switching means is included which is responsive to the high state of an isolated dc signal, having a transistor switch having a collector, an emitter and a base, the collector being coupled to a positive terminal of a ground referenced voltage source. The emitter is coupled to the return of the ground referenced load. The base is coupled to an isolated dc signal.

Abstract: A high frequency ballast circuit powered by a dc input voltage source for starting and operating a gas discharge lamp load, comprising: a means for providing drive signals, each the drive signal having a first and second state, a series switch having a conduction channel having a first and second terminal, the series switch having a control terminal responsive to the drive signals, the conduction channel is on (conductive) in responsive to the interval characterized by the first state of the drive signal and off (non-conductive) in response to a drive signal having a second state, and an inductor. A clamp diode is included. The inductor is coupled to the clamp diode cathode and to the series switch. A ballast reactance is included with a a power oscillator circuit, the power oscillator circuit has a transformer having, a primary winding having a first, a second and a center-tap terminal, a drive winding having a first and a second and a center-tap terminal, and an output winding.

Abstract: A memory cell circuit for storing the state of a digital signal on a data bus in response to an address signal. The memory cell has a store cycle with a repeating series of recurring store cycle sequences, each store cycle sequence having a (HIV) high-voltage timing signal during a first interval, and first and second store timing signals. The memory cell circuit also has a recall cycle. Each recall cycle has a memory reset signal to pre-set the state of the memory cell circuit during a first interval, a recall output signal at a predetermined voltage level and a recall transfer signal. The memory cell comprises a volatile RAM cell having a flip-flop providing an output signal at an output terminal. The flip-flop also has a RESET TERMINAL responsive to a reset signal for forcing the flip-flop to assume a predetermined state in response to the memory reset signal and a SET TERMINAL responsive to a set signal for setting the state of the volatile RAM cell in a recall sequence.

Abstract: A readout apparatus responsive to clockwise and counter-clockwise counter-rotating light beams that have a frequency difference relatable to the rate of rotation of a ring laser gyroscope, the readout apparatus comprising means for removing a portion of the light beams from the ring of the ring laser gyroscope; means for displacing the removed counter rotating beams to overlap a portion of the light of the removed beams to form a first spot beam having fringe motion characterized by an array of co-parallel alternating stripe regions of high and low intensity light within the spot; a mask having an array of co-parallel, rotated, alternating transparent and opaque stripes; the mask being positioned to direct the fringe motion of the spot beam through the mask, the mask array of alternating and opaque stripes being aligned to form a second spot beam having a moire fringe motion characterized by an array of co-parallel alternating stripe regions of high and low intensity light within the spot moving transverse to

Abstract: An infrared detector and imaging system responsive to the scanned image from an objective lens and scanner system, the infrared detector and imaging system comprising: a detector substrate; a sparsely populated staggered detector array formed on the detector substrate, the detector substrate having a focal plane surface receiving the scanned image from the objective lens and scanner system. A clock means provides clock signals. A control signal means is responsive to the clock signal for providing a sequence of predetermined scanner position signals. A servo responsive to each scanner position signal commands the scanner means to locate the scanned image at predetermined positions on the focal plane. A detector signal integration means receives and integrates an array of detector signals from the sparsely populated detector array.

Abstract: A laser gyroscope output signal generator for increasing the resolution of the gyroscope includes a first output producing means for producing a plurality of output pulses for each gyroscope produced output pulse when the gyroscope is rotated in a first direction for connection to a down count input of a counter. A second output producing means is also provided for producing a plurality of output pulses for each gyroscope produced output pulse when the gyroscope is rotated in an opposite direction for connection to an up count input of said counter.

Abstract: A solid state power controller off-line capacitor divider power supply coupler between an ac voltage source output terminal and neutral terminal, supplying regulated dc voltage levels referenced to the ac voltage source output terminal to a load such as the control and drive circuits of a solid state power controller. The invention circuit comprises an input capacitor having a first and second terminal. The capacitor first terminal is coupled to the ac voltage source neutral terminal. A first diode has an anode and a cathode; the anode is coupled to the capacitor second terminal. A positive filter capacitor has a first and second terminal. The first terminal being coupled to the first diode cathode and the filter capacitor second terminal being coupled to the control and drive circuit reference terminal. The invention circuit has a first positive regulator means with an input terminal, an output terminal and a reference terminal. The input terminal is coupled to the filter capacitor first terminal.

Abstract: An isolated low power thyristor gate drive circuit for driving the gate of a thyristor having an anode and a cathode. The drive circuit is responsive to a signal voltage from a signal source. The signal voltage is sourced with respect to a first reference potential to the low power gate drive circuit. The invention circuit has a dual polarity source (DPS) responsive to the signal source for providing a positive drive signal having a positive polarity with respect to a second reference potential and a negative drive signal having a negative polarity with respect to the second reference potential. A normally open semiconductor device network has a current sink terminal, a current source terminal, and a gate terminal. A normally conducting semiconductor device has a current sink terminal, a current source, and a control terminal.The normally open semiconductor device network current sink terminal is coupled to the thyristor anode.