Abstract: Systems and methods that allow for performing a single transaction that both instructs a device to perform an operation and return the resulting data to a processor without the processor having to send a separate request for the result. In accordance with the systems and methods, a bus controller generates a system bus operation that sends (to the device) a thread identifier and a data request formulated in one thread by a processor that context switches to a second thread.

Abstract: A method and apparatus within a computer processing environment is provided for proxy management of a plurality of memory management units connected to a plurality of processing elements or cores within a unified memory environment. The proxy management system includes a proxy processor, such as a RISC core, and proxy memory management units that translate virtual memory requests generated by each of the processing elements into physical address. If the virtual memory requests can be translated directly into a physical address, then the translation is performed and the memory request proceeds. However, if the virtual address cannot be translated into a physical address by the proxy memory management unit, then the unit alerts the proxy processor to perform a page table lookup to locate the physical address. The lookup updates the table in the proxy memory management unit and the memory access proceeds. Such lookup is transparent to the processing element that generated the memory access.