Abstract: To provide a liquid crystal display device capable of outputting a sound of a sufficiently large volume by use of a liquid crystal cell which displays an image. A liquid crystal display device includes a thin front glass substrate having an outer surface in which a rib is formed on a peripheral portion, a back glass substrate arranged with a predetermined gap from an inner surface of the front glass substrate, in which liquid crystal is sealed in the gap, and a sound source element provided in contact with the front glass substrate.

Abstract: A method of manufacturing a liquid crystal display panel where a image display cell region and a plurality of dummy cell regions are provided on a glass substrate. The dummy cells are formed to monitor the internal pressure of liquid crystal sealed in the image display cell region. Liquid crystal is dropped on the image display cell region and the dummy cell regions and the glass substrate and a second substrate are bonded together. The image display cell and the dummy cells, which have the liquid crystal sealed therein, are formed in the image display cell region and the dummy cell regions, respectively. Based on the results of monitoring states of the dummy cells thus formed, a state of the image display cell is estimated.

Abstract: The present invention provides a semiconductor interconnect structure with improved mechanical strength at the capping layer/dielectric layer/diffusion barrier interface. The interconnect structure has Cu diffusion barrier material embedded in the Cu capping material. The barrier can be either partially embedded in the cap layer or completely embedded in the capping layer.

Abstract: A data recovery circuit employing an oversampling technique. The incoming serial data stream with jitter is oversampled by means of the multiple phases of a reference clock to produce data samples. Each sample is compared to the samples collected with the next clock phase in an edge detector circuit to determine the presence of a data edge. The edge information, representative of the data edge positions, is stored and accumulated in the form of a bit map. A detection/suppression circuit detects and suppresses edges which are not adjacent to any other edge in the edge memory. A selection determination circuit uses the edge information to indicate which sample is the farthest from the data edges. A selection validation circuit validates the selection to avoid false determination due to jitter and skew.

Abstract: The present invention provides an enhanced interconnect structure with improved reliability. The inventive interconnect structure has enhanced mechanical strength of via contacts provided by embedded metal liners. The embedded metal liners may be continuous or discontinuous. Discontinuous embedded metal liners are provided by a discontinuous interface at the bottom of the via located within the interlayer dielectric layer.

Abstract: A method and structure for a composite stud contact interface with a decreased contact resistance and improved reliability. A selective dry etch is used which comprises a fluorine containing gas. The contact resistance is reduced by partially dry-etching back the tungsten contact after or during the M1 RIE process. The recessed contact is then subsequently metalized during the M1 liner/plating process. The tungsten contact height is reduced after it has been fully formed.

Abstract: A high ion energy and high pressure O2/CO-based plasma for ashing field photoresist material subsequent to via-level damascene processing. The optimized plasma ashing process is performed at greater than approximately 300 mT pressure and ion energy greater than approximately 500 W conditions with an oxygen partial pressure of greater than approximately 85%. The rapid ash rate of the high pressure/high ion energy process and minimal dissociation conditions (no “source” power is applied) allow minimal interaction between the interlevel dielectric and ash chemistry to achieve minimal overall sidewall modification of less than approximately 5 nm.

Abstract: A method for forming an alignment mark structure for a semiconductor device includes forming an alignment recess at a selected level of the semiconductor device substrate. A first metal layer is formed over the selected substrate level and within the alignment recess, wherein the alignment recess is formed at a depth such that the first metal layer only partially fills the alignment recess. A second metal layer is formed over the first metal layer such that the alignment recess is completely filled. The second metal layer and the first metal layer are then planarized down to the selected substrate level, thereby creating a sacrificial plug of the second layer material within the alignment recess. The sacrificial plug is removed in a manner so as not to substantially roughen the planarized surface at the selected substrate level.

Abstract: A deskewing circuit configured to receive a main clock signal wherein data bits are misaligned with respect to the main clock signal. A multiphase clock generator coupled to the main clock to generate N/2 clock phases on the rising edge of the main clock and N/2 clock phases on the falling edge. A plurality of n samplers to generate a first set of N/2 sampled signals on the positive phases and a second set of N/2 sampled signals on the negative phases. A corresponding plurality of n phase selectors to determine which phase is the best for each set of sampled signals and generate the two selected signals corresponding to that phase. A control logic block configured to receive a corresponding plurality of n first control signals. A data bus gathering all said selected signals for further processing, wherein said selected signals are aligned with said reference clock but misaligned with respect to each other.

Abstract: A semiconductor device structure is provided which includes a first semiconductor device; a second semiconductor device; and a unitary stressed film disposed over both the first and second semiconductor devices. The stressed film has a first portion overlying the first semiconductor device, the first portion imparting a first magnitude compressive stress to a conduction channel of the first semiconductor device, the stressed film further having a second portion overlying the second semiconductor device, the second portion not imparting the first magnitude compressive stress to a conduction channel of the second semiconductor device, the second portion including an ion concentration not present in the second portion such that the second portion imparts one of a compressive stress having a magnitude much lower than the first magnitude, zero stress, and a tensile stress to the conduction channel of the second semiconductor device.

Abstract: A method is provided for patterning a semiconductor region, which can be heavily doped. A patterned mask is provided above the semiconductor region. A portion of the semiconductor region exposed by the patterned mask is etched in an environment including a polymerizing fluorocarbon, e.g., a chlorine-free fluorocarbon having a high ratio of carbon to fluorine atoms, and at least one non-polymerizing substance selected from the group consisting of non-polymerizing fluorocarbons, e.g. those having a low ratio of carbon to fluorine atoms, and hydrogenated fluorocarbons. The method preferably passivates the sidewalls of the patterned semiconductor region, such that a lower region of semiconductor material below the patterned region can be directionally etched without eroding the thus passivated patterned region.

Abstract: The present invention provides a method for producing a temporary chip carrier for semiconductor chip burn-in test and speed sorting. A multi-layered substrate or card, usually comprised of one of various materials is made by offsetting the conductor-filled vias or holes in the outer few layers with the outer most layer not being filled with a conductor, such that a partially filled via or hole is produced. This effectively produces a smaller surface conductor feature, on which the semiconductor chip is temporarily attached, electrically tested, and subsequently removed using various methods, at forces much lower than normal chip removal processes require.

Abstract: A system for connecting a receiver to a redundant power supply. The power supply units are connected to the receiver by means of a pair of control switches, each being connected in series between one of the power units and the receiver, and each having its intrinsic diode forwardly biased between the power unit and the receiver. A voltage comparator senses which of the power supply units is having the higher potential difference between its high and low potential terminals. The output of the comparator controls the gate of both control switches such that the control switch in series with the sensed power supply unit is conducting while the other one is off. When a reversed polarity is applied to the receiver, the receiver is protected by the intrinsic diode. When at least one of the power supplies is connected with the correct polarity, the receiver is supplied without an appreciable voltage drop and with the lowest possible power losses.

Abstract: A lead free solder hierarchy structure for electronic packaging that includes organic interposers. The assembly may also contain passive components as well as underfill material. The lead free solder hierarchy also provides a lead free solder solution for the attachment of a heat sink to the circuit chip with a suitable lead free solder alloy.

Abstract: A method to effectively deposit multi-component solders while remaining compatible with electroplating solder bumping process. A flip-chip solder bump is formed by using electroplated solder bump technology with the addition of wettable layer of metal or solder. The remainder of the required solder volume is deposited by Injection Molded Solder (IMS) technology. This method will accommodate certain metals, as well as trace amounts of alloying, that would be difficult or impossible to electroplate. The method also allows for electrical test between deposition of the wettable layer of solder and the bulk solder, providing the advantages of a more planar surface for probe contact, with very consistent height, less solder pick-up by the test probe and elimination of the post-probe solder reflow step.

Abstract: A lead free solder hierarchy for use in the second level solder connection of electronic components such as joining an electronic module to a circuit board. An off-eutectic solder concentration of SnCu or SnAg is used for the module side connection. This off-eutectic solder contains sufficient intermetallics to provide the module side connection with a robust second level assembly and rework process. The off-eutectic composition provides an inter-metallic phase structure in the module side fillet during assembly. The inter-metallic phase structure eliminates problems of tilt and collapse during second level assembly and aids in rework by providing a more cohesive joint allowing removal of the columns from the board without simultaneous removal from the module.

Abstract: An electronic package having a solder interconnect liquidus temperature hierarchy to limit the extent of the melting of the C4 solder interconnect during subsequent second level join/assembly and rework operations. The solder hierarchy employs the use of off-eutectic solder alloys of Sn/Ag and Sn/Cu with a higher liquidus temperature for the C4 first level solder interconnections, and a lower liquidus temperature alloy for the second level interconnections. When the second level chip carrier to PCB join/assembly operations occur, the chip to chip carrier C4 interconnections do not melt completely. They continue to have a certain fraction of solids, and a lower fraction of liquids, than a fully molten alloy. This provides reduced expansion of the solder join and consequently lower stresses on the C4 interconnect.

Abstract: Methods to create raised pedestal parts in ceramic substrates sintered under a load. The invention uses a patterned, buried, non-sintering layer that provides the needed transfer of load during the sintering process to the raised or pedestal portion of the substrate while maintaining dimensional control of the metallized features on the surface of the pedestal base. The methods involve cutting channels in the ceramic substrate corresponding in position to the perimeter of the opening in the patterned non-sintering contact sheet. The channels may be cut either before or after the sintering of the ceramic substrates.

Abstract: An apparatus and method to align an invisible light beam sensor, such as an IR sensor, utilizing a visible light beam such as a visible LED or HeNe laser, and provide the ability to visually monitor when the sensor needs adjustment in real time and avoid off line adjustments. Various embodiments synchronize and position both the invisible light beam and the visible light beam to travel the same path to a common desired location.

Abstract: A method for forming a semiconductor device, includes forming a first locally doped semiconductor region of a first conductivity type and a second locally doped semiconductor region of a second conductivity type over an undoped, lower semiconductor region. A first etch is implemented to simultaneously create a desired pattern in the first and second locally doped semiconductor regions in a manner that also provides a first passivation of exposed sidewalls thereof, wherein the first etch removes material from the first and second locally doped regions at a substantially constant rate with respect to one another, and in a substantially anisotropic manner. A second etch is implemented to complete the desired pattern in the undoped, lower semiconductor region in a manner that protects the first and second locally doped regions from additional material removal therefrom.