Abstract: Circuitry for selectively sampling a reference voltage with a capacitor 403 includes a first switch 505a for selectively coupling capacitor 403 to a source of a first reference signal during a first operating phase and a second switch 505b for selectively coupling capacitor 403 to a source of a second reference signal during a second operating phase.

Abstract: A measuring device automatically illuminates a digital indication of the measured value in a color in accordance with the selected measurement range.

Abstract: A system and method of presenting whole and/or segmented presentation files, such as graphics, multimedia and/or video files in any combination, within a combination of table or array formats to create a complete scene from within which such presentation files may be placed, played, downloaded, streamed or viewed, including multi-layer file embedding in JAVA which produces a complete scene within which presentation files may be placed, played, streamed or viewed, in a portable virtual one-page design with viewing capability over the World Wide Web via a Web browser or other graphical user interface, over the Internet via a Web browser or other graphical user interface, or from within word processing, desktop publishing, spreadsheet, database or other presentation applications.

Abstract: A processing system 100 is disclosed which includes a system master 101, a system bus 102 coupled to the master, and a plurality of bus interface circuits 106 coupled to bus 102. A first one of the bus interfaces 106 includes a mapping signal input coupled to the master and a mapping signal output, the first bus interface 106 operable to latch-in at least one first selected address bit presented by the master on the system bus in response to a mapping enable signal received at the mapping signal input from the master 101. A second bus interface 106 is provided coupled to the bus 102 and having a mapping signal input coupled to the mapping signal output of first bus interface 106, the second bus interface 106 operable to latch-in at least one second selected address bit presented by the master 101 on the bus 102 in response to a second mapping enable signal received at the mapping input of the second bus interface 106 from the first bus interface 106.

Abstract: Circuitry 400 remotely controls the power in a computing system. An infrared receiver 401 receives a code transmitted from a remote device 206; Circuitry 402 generates a pulse in response to the code, the pulse emulating an output of a switch 205. A transistor 403 has a control terminal for receiving the pulse and outputting a control signal in response.

Abstract: Apparatus 100 for opening and supporting a collapsible container 101 having a wall and opening for receiving items to be disposed. Apparatus 100 comprises a sheet of high impact plastic having a thickness selected such that when the sheet is coiled to form a helical spring, and inserted into the opening of the container and released, the sheet rapidly uncoils thereby opening the container and applying a firm outward pressure to the container wall.

Abstract: A multivalue dynamic random access memory cell and method therefor are provided. Sense circuitry for sensing a most significant bit (MSB) and a least significant bit (LSB) of a binary data value are coupled to an unsegmented complementary bitline pair. The binary data is represented by a multilevel voltage stored on a storage element in the DRAM cell. A reference signal is provided to the sense circuitry, wherein the reference signal is independent of a precharge on the bitline pair. Cross-coupling elements offset the reference signal in response to the sensing of the MSB, whereby the voltage levels corresponding to the LSB are sensed. Following a read, the multilevel data value is restored on the storage element by a restore/write unit including a programmable voltage supply. The detected MSB/LSB pair are input to the restore/write unit which outputs the corresponding voltage level to the DRAM cell.

Abstract: A method of permanently programming selected cells of dynamic random access memory cell array. First selected cell is programmed to a Logic 1 by grounding a first capacitor plate of the first cell, and applying a programming voltage to a second capacitor plate common to the cells of the array. A dielectric disposed between the first capacitor plate and the second capacitor plate breaks down, thereby shorting the first and second capacitor plates. A second selected cell is programmed to store a Logic 1 by allowing a first capacitor of the second cell to float during a period when the programming voltage is applied to the second capacitor plate.

Abstract: A memory 400 including a memory cell 501 disposed at the intersection of an addressable row and addressable column, memory cell 501 being accessible via a selected one of a pair of wordlines 503a, 503b associated with the row and a selected one of a pair of bitlines 502a, 502b associated with the column.

Abstract: A memory 200 including an array 201 of rows and columns of 2-transistor, 1-capacitor memory cells 301 of the cells of each row coupled to first and second wordlines 303a, 303b and the cells of each column coupled to a pair of bitlines 302a, 302b. Refresh circuitry 208 activates the first wordline 303a plus selected said row and refreshes the cells 301 of that row through a first one of the bitlines 302a of each of the columns. Data access circuitry 202, 204 substantially simultaneously activates the second said wordline 303b of a second selected row and accesses selected cells of the second row through a second one of the bitlines 302b in the corresponding columns.

Abstract: Memory 400 is fabricated as a single integrated circuit chip and includes an array 402 of memory cells and circuitry 404/405/413 for accessing selected memory cells in array 402. At least one local ALU 414 is included for receiving data accessed from selected cells of array 402 and performing a selected operation thereon.

Abstract: A memory 601 comprising a plurality of static random access cell arrays 701, and a plurality of sets of latches 703 each for storing address bits associated with data stored in a corresponding one of the static random access cell arrays 701. Bit comparison circuitry 503 compares a received address bit with an address bit stored in each of the plurality of sets of latches 703 and enables access to a selected one of the static random cell arrays 701 corresponding to the set of latches 703 storing an address bit matching the received bit.

Abstract: A memory cell and structure are implemented to provide a memory system having the advantages of both static and dynamic memories. A dynamic memory cell is implemented using a capacitor to store charge associated with a data value stored in the cell. The storage capacitor is accessible through multiple switches, and each of the switches is coupled to an independent bitline. Because independent bitlines are implemented, one bitline may sense the data value stored within the memory cell, while a second bitline is pre-charged, or refreshed, for a next memory operation to be performed. Thus, as soon as data is provided to the first bitline, any memory cells sharing the second bitline are ready to be sensed and restored even though they are all in the same data memory array. Such sequential operation is not possible with prior art DRAM memory cells because they require a refresh period in which to pre-charge bitlines accessing the same memory location.