Abstract: A DC offset correction method and apparatus. In a DC offset correction loop (100), a DC offset is corrected using a binary search routine or any other digital or analog DC offset correction technique. In this binary search routine, the sign of the offset (138) is used to control a direction in which a digital to analog converter (DAC) (166) is stepped until the least significant bit of the DAC is set. The process is enhanced by opening up the bandwidth of the baseband filters (130) to permit the binary search to be clocked (180) at a higher clock rate. After the correction is established, the filters (130) are reset to normal operating conditions.
Type:
Grant
Filed:
February 29, 2000
Date of Patent:
March 12, 2002
Assignee:
Motorola, Inc.
Inventors:
Keith A. Tilley, Raul Salvi, Enrique Ferrer