Abstract: A method and apparatus for retaining heat at a pin-in-hole rework site on a printed circuit board during solder fountain rework of the board. A preheated heat retention plate is attached to the rework side of the printed circuit board. The heat retention plate covers a substantial portion of the board surface. During rework of the printed circuit board, the heat retention plate minimizes the temperature gradient between the rework site of the printed circuit board and the remainder of the printed circuit board. During the rework, the heat retention plate can be heated by an active heater in order to maintain a constant temperature gradient between the rework site of the board and the remainder of the board. By minimizing the escape of heat from the rework site, the number of solder cycles required to rework the board is decreased, resulting in reduced board rework times and increased board longevity.

Abstract: An electronic circuit and a method of designing the electronic circuit having conductive fill stripes which are electrically attached to the power distribution or to the signal routing of the circuit. Preferably, the conductive fill stripes are electrically attached to the power distribution and are interspersed between the power buses and signal wires on the various metal layers to satisfy the metal density requirements of integrated circuit and chip manufacturing. The conductive fill stripes are added during the design process after the placement of the power distribution and signal routing so that electrical continuity between the conductive fill stripes and the connecting bus, metal density requirements, other design rules and logic verification can be completed as the rest of the chip is designed.

Abstract: The disclosure is directed to a method for identifying and classifying data surface defects on the disks of a rigid disk data storage device. By partitioning each surface into cells and sub-sampling every Nth track, the number and location of defects can be determined. The number of stored defects is then examined to determine whether clusters of contiguous cells exist wherein defect totals exceed a predetermined threshold number. This enables the location of clusters on multiple surfaces to be examined for axial alignment, radial alignment or random occurrence as an indication of the source of damage. To obtain further verification of the data surface condition, the location of a defect cluster can be scanned using a utility that evaluates each track within the defect cluster or area.

Abstract: A functional unit, such as an SRAM, in a single clock chip design that contains a scan path can be clocked on either rising edge and falling edge of the clock. The functional unit includes a clock signal having two phases and a plurality of latches for scanning. Two scan latches are added outside the array of the functional unit. In one clock phase, the two scan latches form a latch pair which is connected to the array at Scan-in side. In the other clock phase, one scan latch is connected to the array at the Scan-in side, and the other scan latch is connected to the array at the Scan-out side. In scan/hold operations, a first control signal for the array which is clocked at the falling edge of the clock leads a second control signal for the array which is clocked at the rising edge of the clock. In ABIST/functional operations, the first control signal for the array which is clocked at the falling edge of the clock trails the second control signal for the array which is clocked at the rising edge of the clock.

Abstract: A cleavable epoxy resin composition suitable for encapsulating electronic chips comprising the cured reaction product of a diepoxide containing a cyclic anhydride curing agent or and an amine promoter.

Abstract: An active clamp circuit for digital circuits includes a first MOSFET serially connected between an upper power supply voltage and an input terminal to be clamped, and a second MOSFET serially connected between a lower voltage power supply and the input terminal. The voltages at the gates of the first and second MOSFETs are held at constant first and second reference voltages by a reference circuit and the first reference voltage at the gate of the first MOSFET is less than the second reference voltage at the gate of the second MOSFET. The first and second reference voltages can be changed by connecting the reference circuit to power supply voltages other than the power supply voltages to which the first and second MOSFETs are connected. The reference voltages can also be varied by adding stages of transistors which act as resistors in parallel to the reference circuit. When the first reference voltage is to be varied, it is recommended that the transistors of opposite type be biased independently.

Abstract: A method and apparatus for improving a thermal response of a (magnetoresistive) MR element. In one embodiment, the thermal response is improved by reducing the heat transfer from the MR element to a shield layer. For example, an insulation layer between the MR element and the shield layer may be a material having a lower thermal conductivity than is conventional. In another embodiment, the thermal response is improved by controlling the heating of the MR element based on feedback signal from the MR element, for example, a thermal signal and/or a magnetic or thermal spacing signal. The controlled heating of the MR element may be provided by a heating element, a write element, and/or MR bias current, for example.

Abstract: An error recovery procedure (ERP) in a storage device such as a rotating magnetic hard disk drive is executed to the last step regardless of the established time-out period for an instruction, thereby more reliably recovering from errors. In accordance with one embodiment of the invention, when a disk drive receives a reset instruction from a host during the execution of an ERP, it executes the ERP until the error is recovered, or to the last step without interrupting the ERP. Further, in accordance with another embodiment of the invention, when a disk drive receives a reset instruction during the execution of an ERP, it stops execution of the ERP and holds the number K of the step which was completed immediately before stopping, and when receiving a retry instruction after that, sequentially executes the ERP from the K+1-th error recovery step.

Abstract: The present invention relates to a method of developing a software system using Object Oriented Technology. The present invention addresses the problem of providing a technical foundation for the development of software applications using Object Oriented Technology and frameworks. The present invention solves this problem with a framework supporting flexible interchange of domain algorithms. The present invention is applicable in the technical field of application development of software systems, e.g., for a business application as Financial or Logistic and Distribution, wherein it is the purpose of frameworks to provide significant portions of the application that are common across multiple implementations of the application in a general manner, easy to extend for specific implementation.