Abstract: A method and structure for a memory structure that includes a plurality of substrates stacked one on another is disclosed. The invention includes a plurality of connectors connecting the substrates to one another and a plurality of memory chip packages mounted on the substrates. The connectors have a size sufficient to form a gap between the substrates. The gap is larger than a height of the memory chip packages.

Abstract: A method and structure for searching a computerized network of databases containing documents uses a web crawler. The web crawler is provided with conceptual guidelines before the searching. The invention summarizes and performs text clustering on the summaries to produce classifications. The text clustering is performed using seeds based on the conceptual guidelines. The invention then provides, through a user interface, the classifications and a query entry to search the classifications and directs (in response to the query entry) the user to one or more of the classifications, such that the user is directed to the classifications (and hyperlinks to the documents) and the user is not provided the documents themselves.

Abstract: An apparatus (and method) for testing a DC isolation resistance of a large capacitance network experiencing voltage stress, adds capacitance and resistance to a large resistance network under test, such that the direct current (DC) isolation resistance may be determined without distortion from the alternating current (AC) components of the circuit. The capacitance that is added is determined based on the capacitance of the object, the resistance of the object, and the resistance of the testing apparatus. In one embodiment, because the precise capacitance of the network under test may be unknown, the testing apparatus and method may utilize an additional large capacitor designed to obviate small fluctuations in the capacitance of the network.

Abstract: A method is provided for reducing the microloading effect in a CVD process for depositing a film on a substrate. This method is particularly useful in a single-wafer CVD reactor. The microloading effect is reduced by identifying a growth-rate-limiting reactant; calculating a dilution factor (the ratio of the gas flow rate of the growth-rate-limiting reactant to the total gas flow rate in the reactor); and adjusting the film growth rate and/or the dilution factor to satisfy a numerical criterion for reducing the microloading effect. The criterion is satisfied when the film growth rate is reduced, or the dilution factor is increased, so that the dilution factor is equal to or greater than a quantity which includes the film growth rate as a factor. The film growth rate and dilution factor may be adjusted independently. The gap between the showerhead and the substrate in the CVD reactor may be adjusted to satisfy the numerical criterion.

Abstract: A DRAM capacitor contact comprised of a silicon oxide layer with a trench having sidewalls and a form in the silicon oxide layer. A dielectric liner is coated on the sidewalls of the trench. A metal layer is then deposited between the sidewalls and polished to form a bit-line. One or more dielectric layers are deposited above the bit-lines and VIAs are formed in these layers. A sidewall is formed in the VIA above the bit-line and the VIAs are extended down to the silicon substrate and filled with a conductive material and planarized, forming the capacitor contact.

Abstract: A process for forming a conductive contact having a flat interface. A layer containing niobium and titanium is deposited on a silicon substrate and the resulting structure is annealed in a nitrogen-containing atmosphere at about 500° C. to about 700° C. By this process, a flatter interface between silicide and silicon, which is less likely to cause junction leakage, is formed on annealing. The step of annealing also produces a more uniform bilayer, which is a better barrier against tungsten encroachment during subsequent tungsten deposition. Larger silicide grains are also formed so that fewer grain boundaries are produced, reducing metal diffusion in grain boundaries. The process can be used to form contacts for very small devices and shallow junctions, such as are required for current and future semiconductor devices.

Abstract: A multi-layer semiconductor circuit comprising a plurality of conductive lines having air as a dielectric between the sides of the conductive lines in a first layer and having a structurally supportive non-metal cap layer at least partially covering the top of the conductive lines in the first layer and separating the air dielectric and conductive lines in the first layer from any subsequent layers. In a multi-layer semiconductor circuit with a plurality of conductive lines, at least the top, the bottom, and the opposite sides of each line are encapsulated by an adhesion-promotion barrier layer, and the barrier layer on the top of each conductive line has an upper surface that is flush with (a) a planar lower surface of a cap layer over the barrier layer, (b) a planar upper surface of a dielectric layer between the conductive lines, or (c) a combination thereof. The dielectric layer between the conductive lines may be air.

Abstract: A conductive contact having an atomically flat interface. The contact includes, in order, a silicon substrate, a highly disordered silicide layer, and a titanium oxynitride layer. The silicide layer is formed of titanium, silicon, and one of the elements tungsten, tantalum, and molybdenum. The interface between the silicon substrate and the silicide layer is atomically flat. The flat interface prevents diffusion of conductive materials into the underlying silicon substrate. The contact is useful especially for very small devices and shallow junctions, such as are required for ULSI shallow junctions.

Abstract: A trench capacitor comprising a substrate, a trench formed in the substrate, and conductive doped germanium or silicon-germanium alloy fill material completely filling the trench. The process for creating the capacitor comprises depositing the conductive doped germanium or silicon-germanium alloy in the trench and in a fill layer over the substrate and annealing the wafer at a temperature at which the fill layer melts and completely flows into the trench but the wafer does not melt. The process further includes depositing a silicon cap layer on top of the fill layer to prevent oxidation of the fill layer. The trench may further include one or more of a buffer layer, a metal layer, and a thermal-stress-reduction layer between the trench walls and the fill material.

Abstract: A damascene interconnect containing a dual etch stop/diffusion barrier. The conductive material of the damascene interconnect is capped with a conductive metal diffusion barrier cap, typically using electroless deposition, and, optionally, with a dielectric etch-stop layer. An optional chemical mechanical polish-stop layer may also be present. The different methods of the invention allow the CMP stop, reactive-ion etch stop, and metal diffusion barrier requirements of the different layers to be decoupled. A preferred conductive material is copper.

Abstract: A method of forming a resist layer of uniform thickness across a surface patterned with a varying density of high aspect ratio features. A selected material layer having an affinity to a resist coat to be applied over the selected material layer is applied to a wafer having a plurality of recesses before applying a resist coat. After the resist coat is applied over the selected material layer, the selected material diffuses partially into the resist coat to condition a portion of the resist coat to be insoluble in the presence of a developer which is applied after the resist coat. Those portions of the resist coat into which the selected material layer has not diffused then are removed by a developer leaving a uniform resist coat thickness across the wafer.

Abstract: A method and apparatus for detecting scratches on a wafer surface. The method comprises the use of a monitor wafer which has a substrate, a first layer deposited on the substrate, and a second layer deposited on the first layer. The first and second layers have contrasting work functions such that when short wavelength light is directed on the monitor wafer, scratches through the second layer can be detected.

Abstract: A process for manufacturing a semiconductor circuit. The process comprises creating a plurality of adjacent conductive lines having a solid fill between the conductive lines; creating one or more layers above the lines and the fill; creating one or more pathways to the fill through the layers; and converting the fill to a gas that escapes through the pathways, leaving an air void between adjacent lines. To protect the lines from oxidation during processing, a related process for encapsulating conductive lines in one or more adhesion-promotion barrier layers may be performed. The encapsulation process may also be practiced in conjunction with other semiconductor manufacturing processes. The processes result in a multi-layer semiconductor circuit comprising conductive lines, wherein the lines have air as a dielectric between them, are encapsulated by an adhesion-promotion barrier layer, or both.

Abstract: A DRAM capacitor contact comprised of a silicon oxide layer with a trench having sidewalls and a form in the silicon oxide layer. A dielectric liner is coated on the sidewalls of the trench. A metal layer is then deposited between the sidewalls and polished to form a bit-line. One or more dielectric layers are deposited above the bit-lines and VIAs are formed in these layers. A sidewall is formed in the VIA above the bit-line and the VIAs are extended down to the silicon substrate and filled with a conductive material and planarized, forming the capacitor contact.

Abstract: A compliant, high-density land grid array connector and the process of making such a connector. The process includes the steps of: (a) forming holes in a supporting substrate; (b) forming threaded sidewalls by tapping the holes; (c) plating the threaded sidewalls to form bellows-like structures; and (d) etching a surface of the supporting substrate after the plating to leave portions of the bellows-like structures protruding past a surface of the substrate. The resulting connector includes a substrate having bellows-like contacts extending from one or both sides for resiliently engaging pads such as those of an LGA module. As an alternative, the holes may be formed as blind holes. Ends of the bellows-like contacts may be roughened. The connector may also be formed by casting the substrate in a mold box having screw-like mandrels followed by steps of mandrel removal, hole plating and surface etching.

Abstract: A structure and process for fabricating a crown capacitor using a tapered etch and chemical mechanical polishing to form a bottom electrode having an increased area and crown is provided. The tapered etch is used to form a trough in an interlevel dielectric, e.g. SiO2, and is performed over contact hole forming a crown-like structure. The trough and, optionally, the crown are then covered by a conductor, which is patterned by chemical mechanical polishing.

Abstract: A trench capacitor comprising a substrate, a trench formed in the substrate, and conductive doped germanium or silicon-germanium alloy fill material completely filling the trench. The process for creating the capacitor comprises depositing the conductive doped germanium or silicon-germanium alloy in the trench and in a fill layer over the substrate and annealing the wafer at a temperature at which the fill layer melts and completely flows into the trench but the wafer does not melt. The process further includes depositing a silicon cap layer on top of the fill layer to prevent oxidation of the fill layer. The trench may further include one or more of a buffer layer, a metal layer, and a thermal-stress-reduction layer between the trench walls and the fill material.

Abstract: A multi-film damascene metal interconnect line for a semiconductor device and the method for manufacturing the interconnect line. The interconnect line has a redundant layer film included within the top surface of the interconnect line which reduces stress voiding and electromigration. The interconnect line is produced by depositing a redundant film part-way through the deposition of the bulk metal film and does not require additional polishing steps.

Abstract: Disclosed are shielding platters for semiconductor wafers, and more particularly a reactive ion etch (RIE) chamber wafer masking system, wherein a mechanical mask facilitates the implementation of multiple etches on a single semiconductor wafer.

Abstract: The propagation of a crack from the surface of the dielectric layer of an integrated circuit, through to the underlying circuit elements, is prevented by controlling the interface between the outermost, dielectric layer or layers and the inner layer or layers of the integrated circuit construction. The interface is weakened so that a crack that encounters the interface is caused to propagate in a horizontal manner, along the interface, preventing propagation of the crack in a direction that would be harmful to the manufactured article. This is preferably accomplished with multiple layers of material, each of which is made capable of redirecting (deflecting) the crack. Deflection of the crack, and arrest of the deflected crack along the interface, is made possible by controlling the fracture resistance of the interface.