Abstract: A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and a metal bonding layer deposited on opposing surfaces of the first and second wafers at designated locations to establish electrical connections between active IC devices on the first and second wafers and to provide metal bonding between the adjacent first and second wafers, when the first wafer is pressed against the second wafer using a flexible bladder press to account for height differences of the metal bonding layer across the opposing surfaces of the first and second wafers.

Abstract: An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer comprising a porous matrix, as well as a porogen in certain variations, is formed adjacent a sacrificial dielectric layer. Subsequent to other processing treatments, a portion of the sacrificial dielectric layer is decomposed and removed through a portion of the porous matrix using supercritical carbon dioxide leaving voids in positions previously occupied by portions of the sacrificial dielectric layer. The resultant structure has a desirably low k value as a result of the voids and materials comprising the porous matrix and other structures. The composite dielectric layer may be used in concert with other dielectric layers of varying porosity, dimensions, and material properties to provide varied mechanical and electrical performance profiles.

Abstract: A mechanism and method are provided for assembling a printed circuit board having a first surface, a second surface and an edge. The printed circuit board may include at least one female member to receive a corresponding male member. The mechanism may include an extension board having an edge to couple to the edge of the printed circuit board. The extension board may include a male member to extend from the edge of the extension board and to couple to the at least one male member so as to couple the extension board to the printed circuit board.

Abstract: A method is provided for fabricating an SOI water. This may involve forming a silicon substrate and implanting oxygen into the substrate. Damaged portions of the implanted silicon may be healed/cured by CMP or anneal, for example. An epi layer may then be deposited over the healed/cured regions of the substrate. The substrate may then be annealed to form an insulative layer. The wafer may be thinned to provide the proper thickness of the epi layer.

Abstract: A method of manufacturing liquid crystal devices on a silicon substrate is disclosed. Such a method is accomplished by preparing a silicon substrate having a plurality of die arranged in an array with scribe streets between the dies, and alignment marks within designated scribe streets; preparing a glass substrate having scribe lines, alignment marks within designated scribe lines and openings for filing liquid crystal; attaching the glass substrate to the silicon substrate using the alignment marks on the glass substrate and on the silicon substrate to form a silicon-glass assembly; filling liquid crystal, via the openings on the glass substrate, into a cell gap of each die on the silicon-glass assembly, and sealing the openings on each die to form a liquid crystal device; and separating liquid crystal devices from the silicon-glass assembly along the scribe lines on the glass substrate.

Abstract: A method is provided for creating a polish pad. This may involve determining a design layout of a wafer. The design layout may include a distribution of metal line features on the wafer. A polish pad design may be created/determined based on the determined layer. The polish pad may have asperities having a width greater than a width of metal line features of the wafer.

Abstract: A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and metallic lines deposited on opposing surfaces of the first and second wafers at designated locations with an interlevel dielectric (ILD) recess surrounding the metallic lines to facilitate direct metal bonding between the first and second wafers and establish electrical connections between active IC devices on the first and second wafers.

Abstract: An optical connector comprises an optical circuit and a package casing. The package casing has an integrated modular optical connector, which has multiple optical waveguides.

Abstract: An apparatus for electroless spray deposition of a metal layer on a substrate, e.g., a Co shunt or barrier layer on a Cu layer on a semiconductor wafer, includes a processing chamber to hold the substrate, the processing chamber including at least one section movable between an open position to allow the substrate to be introduced into and removed from the processing chamber and a closed position to seal the processing chamber to allow for pressurization of the processing chamber. The processing chamber has an inlet to provide pressurizing gas, an exhaust line to exhaust pressurizing gas, a pressure regulator to regulate pressure there-within, and a sprayer to spray an electroless plating solution onto the substrate. A method for electroless spray deposition includes providing the in a processing chamber, sealing the processing chamber, pressurizing the processing chamber, regulating the pressure, and spraying an electroless plating solution onto the substrate.

Abstract: A mechanism and method are provided for assembling a printed circuit board having a first surface, a second surface and an edge. The printed circuit board may include at least one female member to receive a corresponding male member. The mechanism may include an extension board having an edge to couple to the edge of the printed circuit board. The extension board may include a male member to extend from the edge of the extension board and to couple to the at least one male member so as to couple the extension board to the printed circuit board.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a gate array architecture. The gate array architecture includes a semiconductor substrate having a plurality of N-type diffusion regions and P-type diffusion regions. The diffusion regions have partially overlying polysilicon landing sites to form N-type and P-type transistors. The regions are relatively sized to form two distinct transistor sizes, smaller N- and P-type transistors and larger N- and P-type transistors.