Abstract: A memory cell comprises a multilayer gate heating structure formed over a channel region between source and drain regions. The multilayer gate heating structure comprises polysilicon and metal silicide layers stacked over a similarly shaped gate oxide. The gate heating structure includes a fusible portion in the metal silicide layer formed over the channel region. In an unprogrammed state, the memory cell operates as a conventional MOS transistor, with current flow between the source and drain regions being controlled by a control voltage applied to the metal silicide layer. However, when a programming voltage is applied across the metal silicide, layer, the fusible portion agglomerates, generating intense localized heating. In an embodiment of the invention, the memory cell is an NMOS device. Tie heating causes segregation of the channel dopant atoms towards the source and drain regions, lowering the threshold voltage of the device.

Abstract: The Intelligent DMA Controller (IDMAC) significantly reduces system latency by replacing one or more layers of software with hardware. The IDMAC uses controlwise and datawise intelligence. The controlwise intelligence of the IDMAC is given specific knowledge of the structure of certain pieces of memory or hardware registers, (e.g. parameter blocks), used for Inter Process Communication. This specific knowledge can be imparted during the design phase of the IDMAC, or dynamically provided during its operation as system requirements dictate. The IDMAC achieves its DMA controlwise intelligence by understanding parameter blocks (PBs). The IDMAC reads the structure of the PB from memory directly, gets all of its PB parameters directly from memory, dereferencing as required, and then begins transferring data between the source and destination as instructed by the PB(s). Examples of PB parameters are source address, destination address, transfer length, and data intelligence opcode.

Abstract: A power-on reset (POR) circuit that delays de-assertion a POR control signal in an IC device such that, when unstable power levels are detected, the POR control signal is maintained in an asserted condition until the IC device is fully reset. During a start-up phase of the IC device operation, the POR control circuit maintains the POR control signal in the asserted condition for a delay period whose length is determined, in part, by the amount of noise in the applied power. After the internal voltage of the IC device achieves a steady state for a suitable period of time, the POR control circuit de-asserts the POR control signal, thereby initiating configuration of the IC device. Subsequently, if a low power condition is detected, the POR control circuit asserts the POR control signal, and maintains the POR control signal in the asserted condition for a pre-defined delay period after the low-power event is detected, thereby allowing the IC device to fully reset.

Abstract: A method is provided to increase the speed of a non-volatile memory transistor by increasing the read channel current in the non-volatile memory transistor. This increase in speed is accomplished without increasing the VCC voltage supply source or decreasing the channel length of the non-volatile memory transistor. The increase in read channel current is accomplished by applying a low voltage to the substrate region of the non-volatile memory transistor, while grounding the source of the non-volatile memory transistor. If the non-volatile memory transistor is located in an array, the low voltage is applied to the sources and drains of non-volatile memory transistors on unselected bit lines to inhibit junction leakage channel current from these unselected non-volatile memory transistors.

Abstract: A decryption scheme is provided for encrypted configuration bitstreams in a programmable logic device. One embodiment includes circuitry for altering a decryption key for a plurality of encrypted bitstream portions, thereby providing a high level of security of the circuit layout embodied in the bitstream.

Abstract: A post-placement residual overlap removal process for use with core-based programmable logic device programming methods that is called when an optimal placement solution includes one or more overlapping cores. Horizontal and vertical constraint graphs are utilized to mathematically define the two-dimensional positional relationship between the cores of the infeasible placement solution in two separate one-dimensional (i.e., horizontal and vertical) directions. Next, the constraint graphs are analyzed to determine whether they include a feasible solution (i.e., whether the overlaps existing in the placement solution can be removed simply by reallocating available resources to the overlapping cores). If one of the constraint graphs is not feasible, then the infeasible constraint graph is revised, and then the feasibility of both graphs is re-analyzed for feasibility. The feasibility analysis and constraint graph revision steps are repeated until both constraint graphs are feasible.

Abstract: A data bus on an integrated circuit includes a series of selectors arranged in a ring, each selector having an output terminal, an enable terminal, a ring input terminal, and a data input terminal. The ring input terminal receives data from another selector in the ring. The data input terminal receives data from a data source. The output terminal supplies data to the ring input terminal of a next selector in the ring. The enable terminal receives enable signals from a data source. A selector either propagates the signal on its ring input terminal or a data signal on its data input terminal to the next selector.