Abstract: A clock distribution network and mechanisms therein for an integrated circuit (IC) including an edge clock and distribution system for same. The invention includes a deskewed clock distribution network for circuits situated in columns wherein buffering is done in columns less than half of the IC length. The mechanism allows each of at least eight vertical column distribution lines to couple with any horizontal clock supply line of at least eight lines. The horizontal clock supply lines include local interconnect inputs. To increase clock source signals, special lines, Kx lines, are provided that are buffered and traverse directionally in 1/4 IC lengths from the top down, bottom up, and midsection both up and down. Kx lines can be sourced from carry signals, IOBs, interconnects, or from an edge clock and supply to clock lines, longlines, or interconnect lines. Kx lines allow vertical signal displacement, e.g., for clock signals, etc., within the chip.