Patents Represented by Attorney Jeanne C. Suchodolski

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  • Semiconductor ROM cell programmed using source mask
    Patent number: 5200802
    Abstract: ROM cell programmed ON has N+ source implant spaced a given distance from the gate with LDD bridging the gap between the N+ source and the N channel. ROM cell programmed OFF has P+ implanted into this gap so as to completely override the LDD in this gap. The P+ prevents the N channel from forming ohmic connection to the N+ source.
    Type: Grant
    Filed: June 22, 1992
    Date of Patent: April 6, 1993
    Assignee: National Semiconductor Corporation
    Inventor: William E. Miller
  • Short circuit detector circuit for memory arrays
    Patent number: 5181205
    Abstract: A method for detecting voltage supply short circuits in integrated circuits and a circuit for implementing that method is disclosed. Entire rows of memory cells in an SRAM are coupled to a single sense line. The sense line to each row is activated individually. The sense lines are in turn coupled to a current sensing circuit. If a short exists on any memory cell in a given row, the current sensing circuit generates a low output, indicating a short circuit.
    Type: Grant
    Filed: April 10, 1990
    Date of Patent: January 19, 1993
    Assignee: National Semiconductor Corporation
    Inventor: Robert A. Kertis
  • Synchronous ECL to CMOS translator
    Patent number: 5130576
    Abstract: An ECL to CMOS translator for BiCMOS circuits. The circuit has a first bipolar transistor which switches the translator from a quiescent state to an active state in the presence of an ECL high level signal. An amplifier driving an NMOS capacitive load amplifies this signal to CMOS levels. Two clock signals reset the circuit to the quiescent state once the ECL high signal has passed. The circuit is kept in the quiescent state by a current source.
    Type: Grant
    Filed: January 16, 1991
    Date of Patent: July 14, 1992
    Assignee: National Semiconductor Corporation
    Inventor: Dennis L. Wendell