Abstract: A circuit for controlling a piezoelectric transducer includes an N-channel FET having a gate electrode, a drain electrode coupled to a high voltage signal source Vpp, wherein Vpp is a positive going pulse train, and a source electrode coupled to an output Vcntrl for controlling the transducer and a charging circuit, responsive to a low voltage input signal Vpp_sel, for charging the FET gate to a bias voltage greater than the FET's threshold voltage while Vpp is near zero volts and for maintaining the bias voltage on the FET gate while Vpp ramps up to a value greater than the bias voltage and until Vpp_sel is removed. The control circuit reduces switching time and reduces current spikes in the power supplies to the chip.