Abstract: A portable computer system wherein the printer port can be used, at the user's option, not only for connection to a printer, but also for connection to an external floppy disk drive. If the BIOS determines that there is an external floppy drive attached, the BIOS disables the normal operation of the parallel port in order to allow the external floppy to operate.

Abstract: A disk drive array with a controller which provides: dynamic remapping for grown defects in the disk drives, multi-thread request processing with a variable number of forkings, defect tracking with both logical and physical lists, guarded writes of less than a full stripe optimized by selectably using the redundancy to limit the number of sectors involved, association of multiple operations with a single disk request in order to facilitate error handling, use of an access hiatus as indication of further opportunity to rebuild data in background, and scatter/scatter (bidirectional scatter/gather) operations.

Abstract: A small computer architecture in which the CPU can receive multiple kinds of interrupt signals, including one kind which is assigned to indicate the occurrence of a keystroke input and another kind which is assigned to indicate the occurrence of a pointing device input. However, the computer does not include any pointing device as such. Instead, the keyboard microprocessor (i.e. a microprocessor other than the CPU) monitors user keystrokes to the computer's keyboard, and: in response to simple keystrokes, or keystroke combinations which include one of the basic chording keys, the keyboard microprocessor sends a keystroke interrupt to the CPU; and in response to keystroke combinations which include an additional chording key, the keyboard microprocessor sends a pointing-device interrupt to the CPU, and provides a data output corresponding to an emulated pointing-device movement.

Abstract: A method and apparatus which provides bi-directional communication between a video monitor and a computer system unit. This enables the video monitor to inform the system unit of its capabilities without direct user involvement and also enables the system unit to directly control or adjust all the functions of the video monitor. In the preferred embodiment, bi-directional communication between the video monitor and the system unit is provided utilizing a mouse port in the keyboard controller. Multiplexors are coupled between the mouse port and each of the mouse and video monitor to select between data paths and selectively allow communication between the system unit and the video monitor. Monitor control software is included in the system unit which can be used to control or adjust the output of the video monitor.

Abstract: An improved read ahead strategy that improves the performance of a disk array subsystem. The disk controller keeps track of the last n reads to the array. If a new read request is received that is adjacent to any of the last n reads, the controller performs a look ahead read because a sequential read may be in progress. The parameter n is preferably set comparable to or greater than the number of maximum independent activites being performed by the computer system. Therefore, in a multithread system, the controller performs a readahead if any one thread is doing a sequential read.

Abstract: A disk array architecture which supports compound RAID configurations and which can automatically switch between various RAID configurations in case of drive failures to prevent data loss and retain data redundancy. In the preferred embodiment, the disk array system of the present invention begins operation with an array configuration that implements a maximum of data redundancy using all of the available disk drives. As drive failures occur, the disk array system automatically reconfigures one or more of the drives to other RAID configurations which utilize less data redundancy and thus require a lesser number of drives. This automatic reconfiguration occurs until the least amount of redundancy remains, or no redundancy remains. In this manner, the disk array system initially takes advantage of all of the available drives for maximum performance and redundancy while still retaining a high level of fault tolerance.

Abstract: A pointing device or mouse which monitors motion in both the X and Y directions as well as in the yaw or rotational direction. The pointing device hence monitors three degrees of freedom and thus provides a more accurate indication of the position of the device. One embodiment comprises a pointing device which includes two motion indicators or mouse balls integrated into the bottom of the device which detect change of motion or position in one X and two Y directions. Separate Y measurements are made for each of the respective balls because yaw or rotation of the device causes the line movements for the two balls to differ. The two balls are preferably a distance L apart, and the rotation and translation of the respective balls are measured by the change in position with reference to a center point between the two balls. The two mouse balls generate signals indicating positive or negative motion in the respective directions.

Abstract: A disk drive array including a controller which provides scatter/scatter (bi-directional scatter/gather) operations between noncontiguous host memory address locations and noncontiguous disk address locations. The host provides a single request to launch a scatter/scatter transfer. The single data request includes a pointer to a list of transfer counts and addresses, the length of the list, and the starting logical address on the disk transfer. Skipped blocks in a scatter/scatter request are specified by data address value of -1, and a no-operation (no-op) request is enqueued for each skipped block. Thus, during reads the controller extends the scattered read from the disk into a single large read of contiguous sectors and suppresses the unwanted data by inserting "no-operation" commands in place of the read commands during the transfer to the host.

Abstract: A battery charging/data transfer structure is provided for use in conjunction with a handheld computer to charge its battery and serve as an infrared data exchange interface between the handheld computer and a data input/output device such as a desktop computer. The structure includes a support housing having an inset well area configured to receive and releasably hold a portion of the handheld computer in a docked orientation. With the handheld computer in this docked orientation a battery charging contact member in the well area contacts a charging area on the received computer portion and transfers battery-charging electrical energy thereto.

Abstract: A method and apparatus which enables devices connected to a bus to detect and take advantage of the early arrival of bus signal inputs. A signal arrival encoder circuit included in a device encodes the arrival time of a signal input whose early arrival is desired to be detected. The arrival time of the signal at issue is categorized according to a desired degree of precision or granularity depending upon the complexity of the encoder used in the respective embodiment. The encoded signal arrival information is then used by the respective device to determine when to sample the other respective input signal. By detecting the early arrival of this input, the device is not required to wait for the worst case signal arrival time to utilize the information. This considerably increases system performance.

Abstract: A memory channel array configuration wherein two or more memory channels are used for data transfer and data is striped across each of the memory channels. In addition, one or more redundant memory channels, preferably a single dedicated parity channel, are used for error correction. In the preferred embodiment the memory channel configuration utilizes RAMBUS based memory channels, and thus the present invention provides error correction for a RAMBUS based memory system. Also, the use of multiple memory channels in conjunction with data striping across each of the channels allows for much higher data transfer bandwidths than is available using prior art implementations of RAMBUS technology.

Abstract: An interconnect sheet for connecting multiple layers of a circuit board for the manufacture of high interconnect density PWBs. The interconnect sheet preferably comprises an area array grid of 0.003 inch solder columns having a 0.006 inch pitch. The interconnect sheet is preferably used to attach two or more multi-layer boards by placing one sheet at every interconnect surface. This interconnect mechanism has an advantage of redundancy of contact and therefore lower susceptibility to failure than other methods. The interconnect sheet of the present invention also offers a large tolerance for registration error without shorting adjacent pads. The preferred method of fabrication of the interconnect sheet begins with creating equally spaced holes through a 0.5 ounce double sided laminate comprising a dielectric sheet and copper plates on either side of the dielectric. These holes are filled with solder paste and the sheet undergoes a baking process to shrink the paste.

Abstract: A memory apparatus using conventional DRAMs which uses a ternary representation of stored data. Each DRAM memory cell can thus store three states. The ternary storage memory apparatus includes a binary to ternary converter which receives a first number of binary bits of data during a write operation and generates a second lesser number of data values or voltages using a ternary representation. A second number of memory storage elements are coupled to the binary to ternary converter and store the respective voltage using the above ternary representation. During reads, a ternary to binary converter reads the voltages stored in the memory elements and converts these voltages into the original first number of binary bits that were originally written into the memory storage elements. This allows the use of existing DRAM while considerably increasing the DRAM's memory storage density.

Abstract: An optimal routing methodology for routing high I/O density packages which minimizes the number of PCB layers required. One feature of this routing methodology comprises treating respective I/O that are routed at the top layer of the package as surface mount technology (SMT) pads without dropping vias within the BGA grid, as is commonplace in the industry. This facilitates the use of fewer escapes and allows for more efficient use of the available space. Signal lines on the top layer of the package which must be routed to other layers of the PCB are connected to vias outside of the area of local high signal density on the printed circuit board. The placement of vias outside the area of local high density, i.e., in a depopulated area, reduces the number of layers necessary in the PCB to properly route the signals. This placement also facilitates the use of filtering capacitors to meet EMI requirements. In addition, all voltage pins are placed on the innermost or outermost grids and have clearanced vias.

Abstract: A parallel port adapter, which provides a special buffering circuit on the four control lines from the system to the printer. This circuit provides a low-impedance bidirectional path for communication between the CPU and the printer, whenever any of the control lines is active. The circuit uses blocking diodes on all four lines, and uses pass transistors in parallel with the blocking diodes, and uses power-robbing to turn on the pass transistors whenever the port is in use.

Abstract: A circuit and method for protecting a voltage inverter circuit is disclosed. The circuit comprises a first comparison circuit capable of comparing a first reference voltage to a voltage indicative of the load current of the voltage inverter. When the comparison circuit signals that the first reference voltage is greater than the load voltage, a disable circuit coupled to the first comparison circuit disables the voltage inverter. In the preferred embodiment, the inverter provides power to a cold cathode fluorescent lamp which, if damaged, can harm the inverter.

Abstract: A personal computer which a microcontroller, separate from the main processor, is used for power-management functions. Under certain conditions, this power-management microcontroller can take control of the system bus. This provide BIOS-independent power management, and permits sophisticated power management to be performed without placing any burden or constraints on the user's choice of operating system or application software.

Abstract: A computer which carries its BIOS in a Flash EPROM. A UV-EPROM carries a redundant BIOS, which can be overlaid onto the BIOS address space by selection with a physical switch.The BIOS contains a small core software program, at the BIOS entry point, which checks BIOS integrity, and provides for reloading the Flash EPROM's BIOS if needed (from a floppy disk, or by copying the entire contents of the UV-EPROM).

Abstract: A content addressable memory (CAM) which is capable of performing string search functions in hardware. The implementation of string search in hardware eliminates the requirement of software to perform this function and thus significantly increases data compression performance. Each byte or memory storage unit of the CAM includes a comparator and a single bit flip-flop. The comparator asserts a match signal to the flip-flop if the contents of a memory storage unit match external data and a prior memory storage unit match signal is asserted. Two types of comparison operations are provided by each memory storage unit. The first ignores the contents of a previous flip-flop, and this comparison operation is used for the first character of a string search. The second type of comparison operation takes into account the value latched in the preceding byte of the CAM. For example, the comparison for byte N only matches if the previous comparison for byte N-1 matched.

Abstract: Using specially designed molded plastic I/O output brackets having differently arranged connection opening series formed therein, a variety of differently configured computers may be manufactured using identical sheet metal chassis. Each bracket has an identical peripheral configuration, is complementarily receivable in an end wall cutout area of any of the chassis, and has a series of I/O connections formed therein which are arranged to complementarily receive the I/O connector devices mounted on the system planar board selected for incorporation within the particular chassis. When the bracket is operatively installed in the cutout area of the chassis wall a peripheral groove formed in the bracket receives an edge portion of the chassis wall and forms therewith an EMI seal having a labyrinth configuration.