Abstract: Methods, apparatus and machine-readable medium to terminate a memory bus line. In some embodiments, the memory bus line is terminated with one or more transistors of an output buffer that are used to drive the memory bus line during a memory write.

Abstract: A gate-clocked domino circuit with reduced leakage current during an inactive state, where domino stages in the domino circuit have long channel length transistors in the pre-charge paths. During an inactive state, the domino stages are put in an evaluation state and are discharged.

Abstract: A method and apparatus for performing modular multiplication is disclosed. An apparatus in accordance with one embodiment of the present invention includes a modular multiplier including a plurality of independent computation channels, where the plurality of independent computation channels includes a first computation channel and a second computation channel, and a coupling device interposed between the first computation channel and the second computation channel to receive a control signal and to couple the first computation channel to the second computation channel in response to a receipt of the control signal.

Abstract: A system, method and medium may delay a strobe signal based upon a delay base and a delay adjustment to reduce effects of process variations and/or environmental changes.

Abstract: Embodiments circuits provide a transistor body bias voltage so that the ratio of ION to IOFF is constant over a range of temperature, where ION is a transistor current when ON and IOFF is a (leakage) transistor current when OFF. In one embodiment, a nFET is biased to provide ION to a current mirror that sources a current AION to a node, a nFET is biased to provide IOFF to a current mirror that sinks a current BIOFF from the node, and an amplifier provides feedback from the node to the body terminals of the nFETs so that at steady state AION=BIOFF, where A and B are constants independent over a range of temperature. In this way, the ratio ION/IOFF is maintained at B/A for some range of temperatures. Other embodiments are described and claimed.

Abstract: A bus architecture arrangement is provided. Embodiments provide for a point-to-point protocol of a bused system, such as a processor-based system. Further embodiments may comprise a dynamically configurable point-to-point communication array with connectors and/or translators to couple hub devices with endpoint devices. Some of the connectors and/or translators may inductively or magnetically couple endpoint devices to and decouple endpoint devices from point-to-point communication media to facilitate efficient use of a point-to-point communication array.

Abstract: A method, apparatus, system, and machine-readable medium to bound data transmission latency by transmitting error verification data at a point during a data transmission based upon loading of a channel for the data transmission is provided. Embodiments may comprise determining the loading of a communication channel and transmitting error verification data to a target device based upon the loading. More specifically, some embodiments transmit error verification data at intervals, variable intervals in some embodiments, to balance transmission latency against the bandwidth available from a communication medium.

Abstract: A memory, such as a register file or a cache, having stack pMOSFETs shared among its word line drivers, where a stack pMOSFET shared by a set of word line drivers has its drain connected to the sources of the pMOSFETs in the set or word line drivers, and were each stack pMOSFET is controlled by an enable signal so as to turn ON only if its corresponding set of word line drivers is enabled. The enable signal may be provided by a write or read enable port, or by the memory's address decoder. The stacked configuration of pMOSFETs significantly reduces sub-threshold leakage current in the word line drivers with very little penalty in performance.

Abstract: A SRAM with reduced subthreshold leakage current, the SRAM including a pMOSFET with its gate at VSS and its source at VCC, and a diode-connected pMOSFET with its source at VCC, where the drains of the pMOSFET and the diode-connected pMOSFET are connected together to provide a voltage VCCL, where VSS<VCCL<VCC. The beta of the diode-connected pMOSFET is substantially larger than the beta of the pMOSFET. The wordline associated with each memory cell is driven to a voltage ?VEE during a read operation, where ?VEE<VSS and VEE?VCC?VCCL. Each memory cell has cross-coupled inverters to store a data bit, where the cross-coupled inverters have pMOSFETs with their sources at VCCL.

Abstract: A system and method for increasing data transfer rate is disclosed. A digital signal waveform that contains one bit of information for every bit time of the digital signal waveform is received. Every three bits of the digital signal waveform is buffered and encoded. The encoding produces an encoded waveform that contains three bits of information for each bit time of the digital signal waveform, therefore, increasing the data transfer rate of the digital signal waveform.

Abstract: Machine-readable media, methods, and apparatus are described which process memory transactions. In some embodiments, a processor or other external components provide a memory controller with decoded memory addresses. The memory controller then may access the memory with the processor decoded address without decoding the address itself. In other embodiments, a processor or other external components provide a memory controller with partially decoded memory addresses. The memory controller then generates a decoded address from the partially decoded address and may access the memory with the generated decoded address.

Abstract: A buffer circuit is provided having a driver device and an input device to receive a first set of signals and to produce a second set of signals. The driver device may receive the second set of signals and output a third set of signals based on the second set of signals input to said driver device. A comparing device may receive the third set of signals from the driver device and produce a fourth set of signals based on the third set of signals, the comparing device may compare the fourth set of signals with the first set of signals.

Abstract: Machine-readable media, methods, and apparatus are described to throttle interfaces and/or logic based upon a temperature estimate. Some embodiments may provide thermal effects associated with throttled and non-throttled interfaces to a filter. The filter may update a temperature estimate based upon the provided thermal effects and one or more thermal time constants. Control logic may determine whether to throttle one or more interface based upon the temperature estimate of the filter.

Abstract: A Snoop Filter for use in a multi-node processor system including different nodes of multiple processors and corresponding processor caches is provided with a Pseudo Least-Recently-Used (PLRU) replacement algorithm to identify a least-recently-used (PLRU) line from the plurality of lines in the cache array for update to reflect lines that are replaced in the processor caches.

Abstract: A cache coherency arrangement with support for pre-fetch ownership, to enhance inbound bandwidth for single leaf and multiple leaf, input-output interfaces, with shared memory space is disclosed. Embodiments comprise ownership stealing to enhance inbound bandwidth and to prevent or attenuate starvation of transactions or of an input-output interface for transactions.

Abstract: A cache coherency arrangement to enhance an upbound path for input-output interfaces is disclosed. Several embodiments may enhance upbound write bandwidth and buffer utilization. Some embodiments may comprise requesting content of a memory granule and merging the content with data associated with a write request for the memory granule prior to satisfaction of an ordering rule associated with the write request. Many embodiments may comprise ownership stealing to enhance inbound bandwidth and to prevent or attenuate starvation and/or deadlock of transactions or of an input-output interface for transactions. Such embodiments may also comprise invalidating merged content of the memory granule. Further embodiments may comprise reverting the merged content to the data associated with the write request.

Abstract: Method and apparatus are described that translate addresses of transactions. A first interface may receive a first address portion of a first transaction and a first address portion of a second transaction. The first address portion may be translated to a second address portion prior to receiving all portions of the first transaction. The first address portion of the second transaction may be translated to a second address portion prior to receiving all portions of the first transaction.

Abstract: An interrupt method, system, and/or medium may comprise generating a load balancing value that helps balance servicing of interrupts among processors.

Abstract: A device to spatially and temporally reorder data a processor, memory and peripherals. This device is able to spatially and temporally reorder data for both write and read operations to and from memory, peripherals and a processor. This device uses a peripheral write path spatial reordering unit and a peripheral write temporal reordering unit to reorder data transmitted to peripherals and the memory. Further, this device users a peripheral read data path spatial reordering unit to reorder data read from peripheral devices. In addition, a main memory spatial reordering unit is utilized to reorder data read from main memory.

Abstract: A computer network is provided for handling ordered transactions between a chipset and a memory controller. The chipset provides an interface with a first bus segment and a second bus segment. The chipset may include logic to attach a destination code to ordered transactions transmitted from the chipset. The memory controller may also include logic to parse the destination code from ordered transactions and apply a fence with respect to a first queue and a second queue of the memory controller.