Abstract: A method for the polarization independent frequency domain equalization (FDE) on polarization multiplexing (POLMUX) coherent systems employing an adaptive crossing FDE which advantageously produces CD compensation, PMD compensation and PolDeMux within one functional block of a digital signal processor (DSP).

Abstract: A programmable optical network architecture and associated components employing a two-level orthogonal frequency division multiplexing (OFDM)/wavelength division multiplexed (WDM) mechanisms for bandwith virtualization.

Abstract: An optical probability-domain LDPC decoder suitable for implementation at 100 Gb/s and above provides large coding gains when based on large-girth LDPC codes. A basic building block, the probabilities multiplier circuit, used to implement both check node and probability node update circuits can be implemented using Mach-Zehnder delay interferometer.

Abstract: A PMD compensation scheme suitable for use in multilevel block-coded modulation schemes with coherent detection.

Abstract: A static, inter-procedural dataflow analysis is used to debug multi-threaded programs which heretofore have been thought unsuitable for concurrent multi-threaded analysis.

Abstract: A system and method is disclosed for formal verification of software programs that advantageously bounds the ranges of values that a variable in the software can take during runtime.

Abstract: An accelerated High-Level Bounded Model Checking method that efficiently extracts high-level information from the model, uses that extracted information to obtain an improved verification model, and applies relevant information on-the-fly to simplify the BMC-problem instances.

Abstract: A method for the static analysis of concurrent multi-threaded software which bypasses the state explosion situation that plagues the prior art, thereby making our method scalable while—at the same time—producing no loss in precision. Our inventive method maintains patterns of lock acquisition and lock release by individual threads by constructing augmented versions of the threads. Once the augmented versions have been constructed, our inventive method verifies the concurrent program using existing tools for the verification of sequential programs—thereby greatly reducing implementation overhead. Finally, our inventive augmentation and method is carried out in an automatic manner—without requiring user intervention.

Abstract: Verification friendly models for SAT-based formal verification are generated from a given high-level design wherein during construction the following guidelines are enforced: 1) No re-use of functional units and registers; 2) Minimize the use of muxes and sharing; 3) Reduce the number of control steps; 4) Avoid pipelines; 5) Chose functional units from “verification friendly” library; 6) Re-use operations; 7) Perform property-preserving slicing; 8) Support “assume” and “assert” in the language specification; and 8) Use external memory modules instead of register arrays.