Abstract: A TDD antenna array S-CDMA system for increasing the capacity and quality of a wireless communications is disclosed. By simultaneous exploiting the spatial and code diversities, high performance communications between a plurality of remote terminals and a base station is achieved without sacrificing system flexibility and robustness. The time-division-duplex mode together with the inherent interference immunity of S-CDMA signals allow the spatial diversity to be exploited using simple and robust beamforming rather than demanding nulling. Measurements from an array of receiving antennas at the base station are utilized to estimate spatial signatures, timing offsets, transmission powers and other propagation parameters associated with a plurality of S-CDMA terminals. Such information is then used for system synchronization, downlink beamforming, as well as handoff management.

Abstract: A computer system and graphics controller which stores video data in memory corresponding to a plurality of video objects and presents the video objects on a video monitor, wherein a plurality of the video objects have differing numbers of bits per pixel formats. System memory stores video data in a plurality of memory areas for each of the plurality of video objects, wherein the plurality of video objects may have differing numbers of bits per pixel. The graphics controller obtains portions of the video data from the plurality of memory areas and in response provides video signals to the video monitor. The computer system and graphics controller performs pointer-based and/or display list-based video refresh operations that enable video object data to be assembled on a per window or per object basis, thereby greatly increasing the performance of the graphical display. The graphics controller maintains pointers to various areas or buffers in system memory comprising video or graphics display information.

Abstract: The present invention comprises an architecture that involves an embedded Digital Signal Processor (DSP), a DSP interface and memory architecture, a micro-controller interface, a DSP operating system (OS), a data flow model, and an interface for hardware blocks. The design allows software to control much of the configuration of the architecture while using hardware to provide efficient data flow, signal processing, and memory access. In devices with embedded DSPs, memory access is often the bottleneck and is tightly coupled to the efficiency of the design. The platform architecture involves a method that allows the sharing of the DSP memory with other custom hardware blocks or the micro-controller. The DSP can operate at full millions-of-instructions-per-second (MIPS) while another function is transferring data to and from memory. This allows for an efficient use of the memory and for a partitioning of the DSP tasks between software and hardware.

Abstract: A graphical programming system and method which includes three-dimensional nodes that are wired or connected to from a graphical program or block diagram. Each of the three-dimensional nodes includes a plurality of sides that are designed to receive pre-defined inputs. In one embodiment, each node includes a left side for receiving data input and a right side for producing output data. The upper or top side of each node is designed to receive inputs regarding error conditions and/or initialization information. The front side of each node is reserved for displaying the name of the node or the function performed by the node. The back side of each node is reserved for timing and synchronization inputs. The bottom side of each node is designed to receive base configuration information and/or type declaration information. The user is only allowed to connect data of the specified type to the designated inputs of each node.

Abstract: A system and method for creating a fieldbus configuration on a computer system. The user assembles a graphical program or wiring diagram on the screen which comprises a selected plurality of function block icons which are linked with one or more wires connecting the function block icons. As the user assembles the fieldbus configuration wiring diagram, the system automatically creates and displays a schedule which visually presents the schedule being created. The schedule comprises one or more schedule bars for graphically or visually indicating the order of execution of the function blocks. The user can change the order of execution indicated by the schedule by graphically manipulating the schedule bars in the schedule. The user can also place one or more loop structures in the editor window which encapsulate a group of function block icons. The loop structure is used to specify a rate for the function block icons comprised within the loop structure.

Abstract: A system and method for multiplexing the data outputs of multiple devices to a data bus using variable size multiplexers that do not require an even 2.sup.N number of inputs. This enables logical groupings of like registers to be more easily and more efficiently multiplexed together. The multiplexing system includes a plurality of registers wherein each register supplies eight bits of data to an eight-bit data bus. Register decode logic receives addresses from the bus and outputs a plurality of register select signals that select the registers during write cycles. The register select signals are also coupled with the outputs of each respective register to form an internal 9-bit bus output from each of the registers. The 9-bit bus internal output from each of the plurality of registers are coupled through one or more layers of multiplexing logic to provide an output to the eight-bit data bus. Instead of using standard 2.sup.N multiplexers with N select lines and 2.sup.

Abstract: A point-to-multipoint bi-directional wide area telecommunications network employing atmospheric optical communication. The network comprises a primary transceiver unit, a plurality of subscriber transceiver units and an optical router. The primary transceiver unit generates a first light beam on which it modulates first data. The primary transceiver unit atmospherically transmits the first light beam to the optical router which demodulates the first data, modulates the first data on a second light beam and transmits the second light beam to the plurality of subscriber transceiver units in multiplexed manner. The subscriber transceiver units receive the second light beam and demodulate the first data from the second light beam.

Abstract: Method and an apparatus for determining a vertical distance between a first marker and a second marker embedded in a formation traversed by a borehole so as to quantify the occurrence of earth layer compaction or subsidence. The markers are implanted within a formation and their relative position is monitored over time to detect the presence of formation subsidence and compaction. A tool having three or more detectors adapted to sense signals emitted from the markers is positioned proximate the markers, where the detectors are separated from each other by a known vertical spacing. The tool is positioned at least at three elevations such that a reference elevation of a reference portion of the tool is determined when (a) the first detector detects a signal emitted from the first marker, (b) the second detector senses a signal emitted from the second marker, and (c) the third detector detects a signal emitted from one of the markers.

Abstract: An autoprobe feature which illustrates the data output of each node as data propagates through a data flow program. As each node in the diagram executes or fires, a routine is invoked which displays the resultant data on the block diagram. Thus, a user can select the autoprobe feature and visually see the data flow out each node as the block diagram executes. Thus, the user can immediately determine if one node is providing incorrect output.

Abstract: A system and method for enabling applications written for SICL driver level software to operate with a VISA system. The present invention maps driver level event function calls from the SICL driver level library to VISA resource operations. This enables a VISA system to operate in conjunction with applications written for the SICL I/O library. The SICL Driver level library provides a completely different methodology for enabling and handling events than does a VISA system. According to the present invention, the method verifies and translate session identifier parameters from SICL functions to corresponding session identifiers in a VISA system. The method also verifies and translates interrupt condition parameters from SICL to corresponding event types in VISA for numerous event functions. Further, the method examines parameters in various SICL event functions and invokes the appropriate VISA operations to perform the indicated functions.

Abstract: A method and apparatus for programming hardware registers using a database defining each hardware register and associated bit fields of the registers, input code including bit field write (BFW) commands identifying bit fields corresponding values to program into the bit fields and defining an array of software copies of the hardware registers, and a preprocessor for writing the appropriate code to program the hardware registers. The database provides the name, size and address of each register and the names and sizes of associated bit fields within each register. The preprocessor generates output source code by replacing the BFW commands with code to manipulate software copies of the hardware registers and to write the software copies to the hardware registers. The output source code identifies each of the affected registers and writing appropriate code to access the register only once per BFW command.

Abstract: A method for representing data types in a graphical program executed by a computer system. The method stores a plurality of executable function icons, scheduling function icons, and data types. A graphical program or data flow diagram is assembled in response to user input utilizing icons which correspond to the respective executable functions, scheduling functions, and data types which are interconnected by arcs or wires on the screen. The wires have different thicknesses, patterns and/or colors to represent the different data types of data being transported on each wire between nodes. The different data types include numerics, booleans, strings, characters, arrays, and structures, among others.

Abstract: A method and apparatus which provides a general solution technique for the integration of traffic measurement and queueing analysis. The frequency-domain approach is used to combine the advanced techniques in two areas: signal processing and queueing analysis. The tool comprises three basic components: traffic measurement, statistical matching and queueing analysis. In the traffic measurement component, standard signal processing techniques are used to obtain the steady-state and second-order statistics of a traffic stream. In the statistical matching component, new techniques are used for the construction of a special class of Markov chain modulated rate processes, the so-called circulant modulated rate process, that can statistically match with each given traffic stream (or superposition of different traffic streams).