Abstract: A graphics system includes a frame buffer that includes one or more memory devices and a frame buffer interface coupled to the frame buffer. Each memory device in the frame buffer includes N banks. Each of the N banks includes multiple pages, and each page is configured to store data corresponding to a portion of a screen region. The frame buffer interface is configured to generate address used to store data corresponding to a frame of data in the frame buffer. The frame includes multiple screen regions. The frame buffer interface is configured to generate addresses corresponding to the data and to provide the addresses to the frame buffer. The addresses are generated such that each of the N banks stores data corresponding to a portion of one out of every N screen regions within a horizontal group of screen regions.

Abstract: A graphics system includes a frame buffer, a write address generator, and a pixel buffer. A burst of pixels received from the frame buffer may not be in display order. In one embodiment, a write address generator calculates a write address for each pixel in the burst of pixels output from the frame buffer. The write address corresponds to a relative display order within the burst for each respective pixel. Each pixel in the burst is stored to its write address in the pixel buffer. This way, the pixels in the burst are stored in display order within the pixel buffer.

Abstract: A method and system for synchronizing data streams and transferring control of resources between two processes in a graphics processor is described. The method allows for completion of pending operations of a first process in a manner that ensures the first process may be restarted without loss of data or process sequence. The processing pipeline is allowed to complete normal execution of all process operations required to reach a first process step that may be interrupted. The second process is initiated when the interruption of the first process is verified. Upon completion of the second process, the first process is reactivated at the next process step in sequence.

Abstract: One embodiment of a method of performing a font operation involves receiving a set of font data identifying a font operation to be performed. If a first font data unit in the set indicates that a first coordinate should be a background color and transparent background is enabled, the method involves outputting an enable for a second font data unit in the set. The second font data unit indicates that a second coordinate should be a foreground color. The enable for the second coordinate is output instead of a disable for the first coordinate. If instead the first font data unit in the set indicates that the first coordinate should be a background color and transparent background is disabled, the method may involve outputting a disable for the first coordinate.

Abstract: A system and method are disclosed for management of sample data to enable video rate anti-aliasing convolution for interlaced video frames. Sample data may be moved simultaneously from a sample buffer to a bin scanline cache and from the bin scanline cache to an array of N2 processor—memory units (e.g., 25 for N=5). Pixel data may be convolved from an N×N sample bin array that may be approximately centered on the pixel location. Since each sample bin contains Ns/b samples, Ns/b×N2 samples may be filtered for each pixel (e.g., 400 for N=5 and Ns/b=16). Each processor—memory unit convolves the sample data for one sample bin in the N×N sample bin array and supports a variety of filter functions. Pixel data may be output to a real time video data stream.

Abstract: A system and method for packing pixels together to provide a increased fill rate in a frame buffer hardware in the graphics system. The graphics system may be configured to receive and rasterize graphics data at a faster cycle rate than the system's frame buffer memory fill rate. The output from the rasterization hardware may be stored in a FIFO memory that is configured to selectively shift pixels in order to improve fill rate performance. The FIFO memory may be configured to ensure that the pixels meet certain criteria in order to prevent page faults and interleave conflicts that could reduce the fill rate. The FIFO memory may also be configured to remove empty cycles that occur as a result of the pixel packing.

Abstract: An improved method and system for detecting differences between first and second test executive sequence files in a computer system. Each of the test executive sequence files may comprise a plurality of interrelated objects. The objects may be compared and differences between the objects may be displayed. The objects may comprise one or more of: a sequence; a global variable; and/or a data type. A sequence may comprise: a step, a parameter, and/or a local variable. A step of a sequence may comprise a tree structure of step properties. Each step property may comprise one or more of: a property value, property flags, and/or a property comment. An object may comprise a hierarchy of objects (e.g., a parent object and a child sub-object). Differences between the hierarchy of objects may be detected. Differences may be navigated. Each displayed difference may be characterized as an insertion or a deletion.

Abstract: A system may include a memory configured to store an attenuation waveform and control logic. The control logic is configured to receive a synchronizing signal indicative of an operating characteristic of a noise source. In response to a value of a characteristic (e.g., frequency) of the synchronizing signal, the control logic is configured to output the attenuation waveform from the memory if the attenuation waveform is associated with that value of the characteristic of the synchronizing signal. An attenuating noise generated dependent on the attenuation waveform attenuates a noise generated by the noise source.

Abstract: A motion control system and method are disclosed which provide improved pulse placement for smoother operation of a motion device such as a stepper motor. A placement of pulses may be determined for each of a plurality of time intervals such that the pulses are placed evenly across the plurality of time intervals, wherein the quantity of pulses in each of the time intervals is variable. The pulses may be generated and sent to the motion device to move the object to the desired position. A delay may be used to place each pulse at an arbitrary location within one of the time intervals. Where the desired step rate is fractional, time may be “borrowed” for one loop iteration from other loop iterations. In one embodiment, the step rate may be changed from one loop period to the next.

Abstract: A system and method for scanning for an object within a region using a conformal scanning scheme. The system may comprise a computer which includes a CPU and a memory medium which is operable to store one or more programs executable by the CPU to perform the method. The method may: 1) determine the characteristic geometry of the region; 2) generate a conformal scanning curve based on the characteristic geometry of the region by performing a conformal mapping between the characteristic geometry and a first scanning curve to generate the conformal scanning curve, i.e., mapping points of the first scanning curve to the characteristic geometry of the region; and 3) scan the region using the conformal scanning curve. These measurements of the region produce data indicative of one or more characteristics of the object. The method may also generate output indicating the one or more characteristics of the object.

Abstract: A graphics system and method for storing and accessing texture maps comprising texels. The graphics system may include a graphics processor and a texture memory comprising a plurality of memory devices for storing the texture maps. The texels (or portions of the texels) may be stored in the memory devices in an interleaved fashion. The texel data is interleaved in the memory devices to guarantee that, no matter which N×M array of texels is accessed, each texel in the array is present in a different memory device or chip and hence are concurrently available. Thus the N×M array of texels may be output concurrently or simultaneously, regardless of which array is accessed, i.e., regardless of which pixel is addressed. Embodiments are also described where the memory devices output arrays of texels for at least two respective neighboring pixels, or a 3D array of texels, in parallel in response to a single read transaction.

Abstract: A video routing system including video routers VR(0), VR(1), . . . , VR(NR−1) coupled in a linear series. Each video router in the linear series successively operates on a digital video stream. Each video router provides a synchronous clock with its output video stream so a link interface buffer in the next video router can capture values from the output video stream in response to the synchronous clock. Each video router buffers a common clock to generate a local output clock. The output clock is used as a read clock to read data out of the corresponding link interface buffer. The output clock is also used to generate the synchronous clock that is transmitted downstream. To initialize the series, reset is sequentially removed from each video router starting from the first video router after the common clock has stabilized.

Abstract: An oscillator circuit. In one embodiment, the oscillator includes a gain circuit, an envelope detector, and an amplitude comparison circuit. The trans-conductance circuit is configured to amplify a periodic signal produced by a crystal. Amplitude peaks of the periodic signal may be detected in the envelope detector, which may determine an average amplitude value based on the detected peaks. The average amplitude value may be compared to a DC voltage value in an amplitude comparison circuit. The DC voltage value may include both a DC average of the periodic signal as well as a predetermined DC offset value. The gain circuit may adjust the level of amplification of the periodic signal based on a feedback signal in order to ensure that the oscillator produces a periodic output signal at a desired level so as to insure oscillation and the minimum use of current to achieve oscillations.

Abstract: A graphics system and method for storing pixel values into or reading pixel values from a sample buffer, wherein the sample buffer is configured to store a plurality of samples for each of a plurality of pixels. The graphics system comprises a sample buffer, a programmable register, and a graphics processor. The programmable register stores a value indicating a method for pixel to sample conversion, and is preferably software programmable (e.g., user programmable). The graphics processor accesses the memory to determine a method for pixel to sample conversion and stores the pixel values in the sample buffer according to the determined method. A first method for pixel to sample conversion may specify a pixel write to all of the pixel's supporting samples. A second method for pixel to sample conversion may specify a pixel write to a selected one of the pixel's supporting samples.

Abstract: A signature capture and analysis system suitable for use in a high performance computer graphics system is described. The system employs a distributed network of signature analysis registers (SARs) which may be configured to capture and accumulate information from one or more channels of data over pre-defined periods of time. The SARs may be so distributed to allow for the isolation of faults to a sub-system level. The signature values developed in these SARs are, in some cases pre-seeded, and may include contributions from both data and control signals. Checking of the signature values against known good or expected outcomes is provided for. In some cases the SARs may be implemented as linear hybrid cellular automatons.

Abstract: A graphics system and method for processing geometry compressed, three-dimensional graphics data are disclosed. After transforming and lighting each vertex, a vertex data stream is decompressed using connectivity information, and vertexes are reassembled into geometric primitives. The connectivity information may include mesh buffer references, vertex tags, or other types of information. Independent buffers, queues, and/or caches are used to simultaneously store: (a) vertex data for the next several primitives, (b) vertex data that will be reused, (c) vertex tags, (d) control tags, (e) vertex data being assembled into a primitive, and (f) an assembled primitive ready to be launched. The assembled primitive may be clip tested for visibility in a defined viewport, before investing time to have the primitive processed into pixel data for display. The independent buffers, queues, and/or caches may also enable the vertex processing steps to be performed in parallel and at different rates.

Abstract: System and method for performing Time Domain Reflectometry (TDR) on a Device Under Test (DUT) using Gaussian pulses. A signal is received comprising an initial Gaussian pulse and one or more reflected pulses from the DUT. Each pulse is characterized by determining a set of estimated parameters, permuting the estimated parameter set to generate one or more permuted parameter sets, generating linear equations from the parameter sets, including parameter variables for the corresponding Gaussian pulse, and determining values for the parameter variables by solving the linear equations. The determined parameters characterize the Gaussian pulse. If there are N parameters to determine and M permutations generated, where M is greater than or equal to N, M+1 linear equations are solved to overdetermine the N parameters. The determined parameters of the initial pulse and the one or more reflected pulses are useable to perform TDR analysis on the DUT.

Abstract: A system and method is disclosed for management of sample data to enable video rate anti-aliasing convolution. Sample data may be moved simultaneously from a sample buffer to a bin scanline cache and from the bin scanline cache to an array of N2 processor—memory units (e.g. 25 for N=5). Pixel data may be convolved from an N×N sample bin array that may be approximately centered on the pixel location. Since each sample bin contains Ns/b samples, Ns/b×N2 samples may be filtered for each pixel (e.g. 400 for N=5 and Ns/b=16). Each processor—memory unit convolves the sample data for one sample bin in the N×N sample bin array and supports a variety of filter functions. Pixel data may be output to a real time video data stream.

Abstract: An optimizing unit for use with an interleaved memory and suitable for use in a computer graphics system is described. The unit utilizes knowledge of the repetitive and predictable nature of texture buffer accesses to potentially reduce the number of memory fetches. The unit maintains a queue of pending requests for tiles of data from the memory, and predicts the retrieval of redundant data within short sequences of requests. The redundant data is retrieved from the memory once, and repeated as necessary from local temporary storage registers.

Abstract: A graphics system may include a frame buffer that includes several sets of one or more memory banks and a cache. The frame buffer may load data from one of the memory banks into the cache in response to receiving a cache fill request. Each set of memory banks is accessible independently of each other set of memory banks. A frame buffer interface coupled to the frame buffer includes a plurality of cache fill request queues. Each cache fill request queue is configured to store one or more cache fill requests targeting a corresponding one of the sets of memory banks. The frame buffer interface is configured to select a cache fill request from one of the cache fill request queues that stores cache fill requests targeting a set of memory banks that is not currently being accessed and to provide the selected cache fill request to the frame buffer.