Abstract: A high voltage MOS transistor with a gate extension that has a reduced electric field in the drain region near the gate is provided. The high voltage MOS transistor includes a first and second gate layers, and a dielectric layer between the gate layers. The first and second gate layers are electrically coupled together and form the gate of the transistor. The second gate layer extends over the drain of the transistor above the dielectric and gate oxide layers to form the gate extension. The gate extension reduces the peak electric field in the drain by providing a wide area for the voltage to drop between the drain and the gate of the transistor. The dielectric layer also reduces the peak electric field in the drain near the gate by providing insulation between the gate and the drain. A lower electric field in the drain reduces the impact generation rate of carriers.

Abstract: A high voltage MOS transistor is provided that is compatible with low-voltage, sub-micron CMOS and BiCMOS processes. The high voltage transistor of the present invention has dopants that are implanted into the substrate prior to formation of the epitaxial layer. The implanted dopants diffuse into the epitaxial layer from the substrate during the formation of the epitaxial layer and subsequent heating steps. The implanted dopants increase the doping concentration in a lower portion of the epitaxial layer. The implanted dopants may diffuse father into the epitaxial layer than dopants in the buried layer forming an up-retro well that prevents vertical punch-through at high operating voltages for thin epitaxial layers. In addition, the doping concentration below the gate may be light so that the threshold voltage of the transistor is low.

Abstract: Circuits and methods for controlling load sharing by multiple power supplies are provided. In preferred embodiments, load share controllers utilize multiple voltage control loops to monitor the output voltages that are being provided by multiple power supplies connected to a load. These voltage control loops each generate a voltage control voltage that is proportional to the difference between the actual output voltage of the corresponding power supply and the desired output voltage. The voltage control loop with the highest voltage control voltage then controls a current control voltage generated in a current control loop for each power supply via a share bus. These current control loops then regulate the current provided by the corresponding power supplies so that those currents are all proportional to the voltage on the share bus.

Abstract: A high voltage MOS transistor is provided that is compatible with low-voltage, sub-micron CMOS and BiCMOS processes. The high voltage transistor of the present invention has dopants that are implanted into the substrate prior to formation of the epitaxial layer. The implanted dopants diffuse into the epitaxial layer from the substrate during the formation of the epitaxial layer and subsequent heating steps. The implanted dopants increase the doping concentration in a lower portion of the epitaxial layer. The implanted dopants may diffuse father into the epitaxial layer than dopants in the buried layer forming an up-retro well that prevents vertical punch-through at high operating voltages for thin epitaxial layers. In addition, the doping concentration below the gate may be light so that the threshold voltage of the transistor is low.

Abstract: The present invention provide systems and methods for reducing a reverse recovery current through a body diode in a synchronous switching transistor. An inductor is coupled in the commutation path of the body diode of the synchronous switching transistor. The inductor slows the rate of increase of the reverse recovery current to reduce avalanche effects in the synchronous switching transistor. This reduces the peak reverse recovery current through the body diode of the synchronous switching transistor when the body diode commutates, thereby reducing power dissipation in the main switching transistor. An inductor may be coupled to both switching transistors so that power dissipation is reduced if the regulator is operated as a buck or boost regulator. A diode and a reverse recovery switcher may be coupled to the inductor to transfer energy in the inductor back to the input or output capacitor after the body diode commutates.

Abstract: Recovery systems and methods of the present invention include circuitry that transfers energy from an input to an output with reduced power dissipation. A synchronous switching regulator is one application for the recovery system of the present invention. An inductor may be used in a synchronous switching regulator to reduce power dissipation caused by reverse recovery current that flows through the body diode of the synchronous switching transistor when the synchronous switching transistor turns OFF. Energy in the inductor may be transferred back to the input or output capacitor of the switching regulator through a recovery system of the present invention. The recovery circuit of the present invention provides an efficient method for intercepting energy in the inductor, and presenting power to a recovery switcher in a manner that allows the recovery switcher to transfer the energy into the input or output capacitor of the switching regulator efficiently.

Abstract: A high voltage MOS transistor with a gate extension that has a reduced electric field in the drain region near the gate is provided. The high voltage MOS transistor includes a first and second gate layers, and a dielectric layer between the gate layers. The first and second gate layers are electrically coupled together and form the gate of the transistor. The second gate layer extends over the drain of the transistor above the dielectric and gate oxide layers to form the gate extension. The high voltage MOS transistor of the present invention may be fabricated without additional processing steps in BiCMOS and CMOS processes that use dual polysilicon layers and a dielectric layer that are used to form capacitors.

Abstract: Circuits and methods for controlling load sharing by multiple power supplies are provided. In preferred embodiments, load share controllers utilize multiple voltage control loops to monitor the output voltages that are being provided by multiple power supplies connected to a load. These voltage control loops each generate a voltage control voltage that is proportional to the difference between the actual output voltage of the corresponding power supply and the desired output voltage. The voltage control loop with the highest voltage control voltage then controls a current control voltage generated in a current control loop for each power supply via a share bus. These current control loops then regulate the current provided by the corresponding power supplies so that those currents are all proportional to the voltage on the share bus.