Patents Represented by Attorney, Agent or Law Firm Jeffrey K. Weaver
  • Patent number: 7430477
    Abstract: In particular, this invention provides novel methods of populating data structures for use in evolutionary modeling. In particular, this invention provides methods of populating a data structure with a plurality of character strings. The methods involve encoding two or more a biological molecules into character strings to provide a collection of two or more different initial character strings; selecting at least two substrings from the pool of character strings; concatenating the substrings to form one or more product strings about the same length as one or more of the initial character strings; adding the product strings to a collection of strings; and optionally repeating this process using one or more of the product strings as an initial string in the collection of initial character strings.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: September 30, 2008
    Assignee: Maxygen, Inc.
    Inventors: Sergey A. Selifonov, Willem P. C. Stemmer
  • Patent number: 7421347
    Abstract: “In silico” nucleic acid recombination methods, related integrated systems utilizing genetic operators and libraries made by in silico shuffling methods are provided.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: September 2, 2008
    Assignee: Maxygen, Inc.
    Inventors: Sergey A. Selifonov, Willem P. C. Stemmer, Claes Gustafsson, Matthew Tobin, Stephen del Cardayre, Phillip A. Patten, Jeremy Minshull
  • Patent number: 7058515
    Abstract: “In silico” nucleic acid recombination methods, related integrated systems utilizing genetic operators and libraries made by in silico shuffling methods are provided.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: June 6, 2006
    Assignee: Maxygen, Inc.
    Inventors: Sergey A. Selifonov, Willem P. C. Stemmer, Claes Gustafsson, Matthew Tobin, Stephen del Cardayre, Phillip A. Patten, Jeremy Minshull, Lorraine J. Giver
  • Patent number: 6618084
    Abstract: Disclosed is a fault tolerant CMOS image sensor that includes circuitry for identifying defective pixels and masking them during image generation. Masking may involve, in one example, replacing the output of a given pixel with an average of the output of surrounding non-faulty pixels. Thus, while image sensors may be fabricated with some number of faulty pixels, the images produced by such sensors will not have undesirable bright or dark spots. The disclosed sensor includes (a) one or more pixels (active or passive) capable of providing outputs indicative of a quantity of radiation to which each of the one or more pixels has been exposed; and (b) one or more circuit elements electrically coupled to the one or more pixels and configured to identify and correct faulty pixels in the CMOS imager. The one more pixels each include a photodiode diffusion formed in a well and a tap to power or ground also formed in the well.
    Type: Grant
    Filed: November 5, 1997
    Date of Patent: September 9, 2003
    Assignee: STMicroelectronics, Inc.
    Inventors: Roberto Rambaldi, Marco Tartagni, Alan H. Kramer
  • Patent number: 6504572
    Abstract: Disclosed is a CMOS image sensor that includes circuitry for identifying defective pixels, particularly pixels having leaky access switches. The leaky access switches allow charge to escape from the pixel over a row or column line in a pixel array, thereby corrupting the outputs of an entire row or column of pixels. A disclosed test involves (a) electronically setting a defined charge in a selected pixel of the CMOS imager; (b) reading the output of the selected pixel; and (c) comparing the output of the selected pixel to an expected value based upon the defined charge set in the selected pixels. If the output significantly deviates from the expected value, then the selected pixel is identified as having a leaky access switch. Preferably, a newly fabricated sensor is first tested as described. If such leaky access switch is discovered, the imager is discarded without incurring further manufacturing cost.
    Type: Grant
    Filed: November 5, 1997
    Date of Patent: January 7, 2003
    Assignee: STMicroelectronics, Inc.
    Inventors: Alan H. Kramer, Roberto Rambaldi, Marco Tartagni
  • Patent number: 6501030
    Abstract: A grounding plug structure configured for push-type snap lock fastening in circuit board screw holes is provided with a resilient deformable conductive member. When a circuit board with one or more such plug structures fastened thereto is mounted with respect to a tray or chassis, the conductive portion of the plug structure is deformed against a surface of the tray, forming an effective conductive pathway, e.g., for grounding, between the tray and the circuit board. In this way, grounding pathways can be established while eliminating the need for at least some screw mounting and/or standoff structures.
    Type: Grant
    Filed: October 26, 1999
    Date of Patent: December 31, 2002
    Assignee: Cisco Technology, Inc.
    Inventors: Bobby Parizi, Nguyen Tu Nguyen, Saeed Seyedarab, Toan Nguyen
  • Patent number: 6233012
    Abstract: A circuit technique to reduce the input capacitance line of a charge integrator is described. This approach is particularly tailored for embedded read-out circuits in solid-state integrated sensors. An integrated charge amplifier described herein includes a generic amplifier element and a high speed buffer which drives a metal shield placed underneath the input line. The metal shield therefore follows the potential of the input line and thereby reduces the capacitance between the input line and ground.
    Type: Grant
    Filed: November 5, 1997
    Date of Patent: May 15, 2001
    Assignee: STMicroelectronics, Inc.
    Inventors: Roberto Guerrieri, Marco Bisio, Marco Tartagni
  • Patent number: 6188056
    Abstract: Disclosed is a CMOS image sensor that includes pixels employing a radiation-sensitive resistive element in which the resistance of the element changes in response to the quantity of radiation striking it. The resistive elements are made from an appropriately doped polycrystalline semiconductor material such as polysilicon. The pixels are provided on a semiconductor device in which the photosensitive resistive elements are provided on a first layer and the pixel associated transistors are provided on a second layer. The fill factor may be approach 100 percent for such pixels.
    Type: Grant
    Filed: June 24, 1998
    Date of Patent: February 13, 2001
    Assignee: STMicroelectronics, Inc.
    Inventors: Alexander Kalnitsky, Frank Randolph Bryant, Marco Sabatini
  • Patent number: 6188969
    Abstract: A computer-implemented statistical technique is provided for normalizing the response curves of multiple measurement methods. The end result is a group of response curves, one for each measurement method under consideration, which depend on a common independent variable—the actual physical property being measured by the methods. The results are provided as a collection of equations, curves, and/or tables (a “nomogram”) to facilitate conversion of measured values from one method to measured values from a second method. In the technique, data is provided for each of the methods being normalized. The input data includes measured values from common samples which are analyzed by two or more of the methods under consideration. The technique also requires assumptions or approximations of the true physical property values for each of the samples used to generate the data. Still further, the technique requires assumptions of the mathematical form of the response curves (e.g., linear, sigmoidal, etc.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: February 13, 2001
    Assignee: Chiron Corporation
    Inventor: James M. Minor
  • Patent number: 6133864
    Abstract: A parallel pipelined analog-to-digital converter for use with chips containing large arrays of detectors is described. In these A/D converters, the degree of parallelism decreases between earlier and later pipeline stages. That is, there are fewer instances of at least one of the later stages than there are instances of at least one of the earlier stages. Thus, the instances of the earlier stages are responsible for processing a fewer number of pixels than are instances of the later stages. Viewed another way, the parallel pipelined analog-to-digital converter architecture of this invention assumes a tree or branched arrangement in which the earlier stages correspond to leaves and the later stage condense to branches. In an extreme example, the later stages coalesce to a single route.
    Type: Grant
    Filed: April 1, 1998
    Date of Patent: October 17, 2000
    Assignee: STMicroelectronics, Inc.
    Inventor: Marco Sabatini
  • Patent number: 5981932
    Abstract: Disclosed is a method and associated apparatus for compensating for kTC noise in individual pixels of an MOS imaging array. The kTC noise at issue forms when a pixel is disconnected from a reset voltage by turning off an MOS transistor which controls access to the pixel photodiode. Compensation is accomplished by first exposing the photodiode to the reset voltage and then disconnecting the well region from V.sub.dd to cause it to float. By allowing the well to float, the kTC charge subsequently introduced (at the conclusion of the reset process) redistributes so that most of it accumulates on the capacitor between the well and the substrate. Later, the well is reclamped to V.sub.dd, and the noise contribution stored in the well-substrate capacitor is canceled. A disclosed apparatus includes an array of pixels, each having a separate well. In addition, access of the well to a source of power (V.sub.dd) must be switchable. Therefore, a transistor is included at each pixel's connection to a V.sub.dd.
    Type: Grant
    Filed: November 5, 1997
    Date of Patent: November 9, 1999
    Assignee: STMicroelectronics, Inc.
    Inventors: Roberto Guerrieri, Roberto Rambaldi, Marco Tartagni
  • Patent number: 5982676
    Abstract: Disclosed is an electrical technique for clamping the bitline voltage above zero volts in a DRAM circuit. The technique may be used in embedded DRAM arrays implemented in logic-based technology employing low threshold voltages. The invention employs a low voltage generator to provide a bitline voltage slightly above zero volts. Applying this slightly elevated level to the input of a DRAM cell access transistor effectively increases the threshold voltage of that transistor and thus limits sub-threshold leakage current. The low voltage generator may be implemented as a cascode circuit with supplemental current sources.
    Type: Grant
    Filed: May 26, 1998
    Date of Patent: November 9, 1999
    Assignee: STMicroelectronics, Inc.
    Inventors: Pavel Poplevine, Alexander Kalnitsky
  • Patent number: 5973985
    Abstract: Disclosed is a multiport SRAM cell. The cell state may be switched by controlling the potential on a single bit line only. A true dual port SRAM cell (in which the two ports may be accessed nearly simultaneously without needing peripheral arbitration logic) employs two cross-coupled inverters, two bit lines, two word lines, and two access transistors. The SRAM cells employ internal "pseudo inverters" that can be independently powered on and off. By powering one of them off during the write operation, the internal conflict associated with changing the value of a stored bit is avoided. Each pseudo inverter may be powered on and off via a pseudo ground or a pseudo Vdd line which controls the potential to locations where ground or Vdd are normally supplied to CMOS inverters.
    Type: Grant
    Filed: August 11, 1998
    Date of Patent: October 26, 1999
    Assignee: STMicroelectronics, Inc.
    Inventor: Richard J. Ferrant
  • Patent number: 5578145
    Abstract: A method for fabricating a composite cladding comprised of a moderate-purity metal barrier of zirconium metallurgically bonded on the inside surface of a zirconium alloy tube which improves corrosion resistance. The improved corrosion resistance of the liner is accomplished by suitable heat treatment of the Zircaloy-zirconium composite cladding to allow diffusion of alloying elements, notably Fe and Ni, from the Zircaloy into the zirconium, in particular, to the inner surface of the zirconium liner. This diffusion anneal reduces the undesirable tendency of zirconium liner to oxidize rapidly.
    Type: Grant
    Filed: December 14, 1994
    Date of Patent: November 26, 1996
    Assignee: General Electric Company
    Inventors: Ronald B. Adamson, Daniel R. Lutz
  • Patent number: 5572673
    Abstract: A database management system is provided for security of database objects. These objects may be passive elements such as tables, rows, views, the databases themselves, etc., or they may be executable items such as stored procedures or triggers. A mechanism is provided for "certifying" that certain types of objects such as stored procedures, triggers, and views can be safely used to access other, sensitive objects in the database. Certification indicates that (1) a security officer has evaluated and certified the object, and (2) the now certified object has not undergone a defined security-relevant change since certification. Certification is particularly important in the context of a "trusted" stored procedure or a "trusted" stored trigger. "Trusted" executable objects can be executed at sensitivity levels that exceed that of a user or subject. Thus, the subject may use a trusted stored procedure or trigger to access certain objects having higher sensitivity levels than his or her own.
    Type: Grant
    Filed: December 1, 1993
    Date of Patent: November 5, 1996
    Assignee: Sybase, Inc.
    Inventor: Scott A. Shurts
  • Patent number: 5524032
    Abstract: A cladding tube having a cross-section and including (1) a zirconium alloy outer circumferential substrate having an inner surface and having one or more alloying elements, (2) a zirconium barrier layer bonded to the inner surface of the outer circumferential substrate and being alloyed with the one or more alloying elements, and (3) a zirconium alloy inner circumferential liner bonded to the inner surface of the zirconium barrier layer. The barrier layer will have a concentration profile including a diffusion layer extending from the barrier layer's inner surface (facing nuclear fuel) to the barrier layer's interior (between the barrier layer's inner and outer surfaces). At the interior edge of the diffusion layer, there will be substantially no alloying elements. At the outer edge of the diffusion layer (the barrier layer's inner surface), the maximum concentration of alloying elements will occur.
    Type: Grant
    Filed: March 21, 1994
    Date of Patent: June 4, 1996
    Assignee: General Electric Company
    Inventors: Ronald B. Adamson, Daniel R. Lutz, Joseph S. Armijo, Herman S. Rosenbaum
  • Patent number: 5519748
    Abstract: A Zircaloy cladding having an outer region comprising fine precipitates and inner region comprising coarse precipitates is provided. The outer region comprises about 10% and the inner region comprises about 90% of the cladding wall thickness. Such Zircaloy tubing is resistant to propagation of cracks and at the same time resistant to corrosion in boiling water reactors (BWR). Resistance to damage caused by the pellet-cladding-interaction can be achieved by standard application of a zirconium or zirconium-alloy liner on the tubing inside surface.
    Type: Grant
    Filed: April 23, 1993
    Date of Patent: May 21, 1996
    Assignee: General Electric Company
    Inventors: Ronald B. Adamson, Gerald A. Potts
  • Patent number: 5517541
    Abstract: The present invention provides a cladding having an outer circumferential substrate, a zirconium barrier layer metallurgically bonded to the inside surface of the substrate and an inner circumferential liner metallurgically bonded to the zirconium barrier. The inner circumferential liner is more ductile than conventional Zircaloy. The low ductility of the inner circumferential liner is obtained, for example, by using a zirconium alloy containing a low tin content (e.g. less than 1.2% by weight) and/or a low oxygen content (e.g. less than 1000 ppm). The inner circumferential liner is less than about 25 micrometers thick.
    Type: Grant
    Filed: May 10, 1994
    Date of Patent: May 14, 1996
    Assignee: General Electric Company
    Inventors: Herman S. Rosenbaum, Joseph S. Armijo
  • Patent number: 5517540
    Abstract: A method is provided for preparing a cladding tube having an outer substrate, an intermediate zirconium barrier layer, and an inner liner. The method includes the following steps: (a) bonding an inner liner alloy sheath exterior circumferential surface to a zirconium sheath interior circumferential surface to form a barrier/inner liner sheath, and (b) bonding the exterior surface of the zirconium sheath on the barrier/inner liner sheath to the interior circumferential surface of an outer substrate alloy tube to form the cladding tube. Alternatively, the method includes the following steps: (a) bonding the zirconium sheath exterior circumferential surface to the outer substrate alloy tube interior circumferential surface to form a substrate tube/barrier sheath, and (b) bonding the exterior circumferential surface of the inner liner alloy sheath to the interior circumferential surface of the zirconium sheath of the substrate tube/barrier sheath to form said cladding tube.
    Type: Grant
    Filed: March 21, 1994
    Date of Patent: May 14, 1996
    Assignee: General Electric Company
    Inventors: Mickey O. Marlowe, Joseph S. Armijo, Cedric D. Williams, Herman S. Rosenbaum
  • Patent number: 5475723
    Abstract: A cladding tube for use in holding fissionable material in a water cooled nuclear reactor is provided. The cladding tube includes inner and outer circumferential regions, and including (1) a substrate defining the outer circumferential region, and (2) an inner liner defining the inner circumferential region. The inner liner is made from a zirconium alloy having at least one alloying element which promotes hydrogen absorption in a concentration of between about 1 and 15 weight percent. The hydrogen absorption promoting element can be one of the following: nickel, chromium, iron, zinc, vanadium, gallium, yttrium, palladium, platinum, or aluminum.
    Type: Grant
    Filed: March 21, 1994
    Date of Patent: December 12, 1995
    Assignee: General Electric Company
    Inventor: Mickey O. Marlowe