Abstract: A fuse (12) detonates a spin-stabilized projectile (10) after the fuse (12) experiences a preset number of turns. The preset number is communicated (64) to the fuse (12) prior to launch. A semiconductor piezoelectric strain gauge (26) senses stress and provides a signal which is responsive to centrifugal forces experienced by the sensor (26) as a result of projectile spin. A microcontroller (30) repetitively digitizes and translates the sensor signal to determine turn numbers, which the microcontroller (30) integrates to determine the total number of turns experienced by the fuse (12) since launch. When the accumulated turn number reaches (94) the preset number, the fuse (12) detonates the projectile (10). However, an arming duration (76) must have expired before the projectile (10) can detonate, and the projectile (10) can detonate at any time following the expiration of the arming duration when an impact is detected.

Abstract: A numerically controlled oscillator (NCO) (10) or direct digital synthesizer (DSS) includes a phase accumulator (12, 28, 30), a phase to amplitude converter (24), and a digital to analog converter (26). The phase accumulator is partitioned into a high speed phase accumulator stage (44) and a low speed phase accumulator stage (46). The high speed stage (44) performs modulo accumulation on the most significant N.sub.M bits of the entire phase word. The low speed stage (46) performs modulo accumulation on the least significant N.sub.L bits of the entire phase word. The low speed stage (46) supplies a carry signal to the high speed stage (44). The low speed stage (46) operates with an accumulation period that is 2.sup.X times slower than the accumulation period for the high speed stage (44). A phase output is taken from the most significant N.sub.p of the N.sub.M bits accumulated in the high speed stage (44), where desirably N.sub.M .gtoreq.N.sub.p +X.

Abstract: A method and apparatus to dynamically allocate instructions to programmable processing element decoders (78, 79, 80) in a SIMD processor (100) includes a source code instruction (71) for the processor is parsed (1) into components (75, 76, 77) that apply to specific processing elements (60, 61, 62). The components (75, 76, 77) are used to determine control signals (90, 91, 92) that must be generated from the processing element instruction decoders (50, 51, 52) in order to execute the given instruction. If a processing element instruction decoder (50, 51, 52) is not capable of producing the necessary control signals (90, 91, 92), the decoder (50, 51, 52) must be reconfigured to do so. Then the processing element instruction (75, 76, 77) that will generate the specified control logic can be determined and returned to the assembler or compiler so that the assembly or compilation of the program can be completed.

Abstract: A pseudorandom noise coded system (100) compensates for imperfections, improving out of range rejection, and includes a digital correlator (200) having a first complex multiplier (202) receiving a sequence of sampled data words and a sequence of precomputed complex data words and producing a sequence of first complex product words. A second complex multiplier (204) receives the sequence of first complex product words and a precomputed constant word and produces a sequence of second complex product words. A complex multiplexer (206) receives a sequence of binary code states, and the sequences of first and second complex product words and produces a sequence of complex multiplexer output words formed as a replica of either the first or the second complex product words, depending on the binary code. A complex accumulator (208) receives the sequence of complex multiplexer output words and produces a complex accumulated sum word formed as a complex sum of the complex multiplexer output words.

Abstract: A method and apparatus for hardening current steering logic (CSL) to soft errors (charged particles passing through and upsetting the logic state of an integrated circuit) includes a hardened CSL circuit or cell (20), including three or more circuit cell elements (21) in parallel. The circuit cell elements (21) redundantly perform a single cell function. Each of the circuit cell elements (21) is coupled to soft error immune resistive elements (24 and 25) within a summing element (22). Current (23) is steered through the resistive elements (24 and 25) depending upon input signals (26) to each of the circuit cell elements (21). The logical output signal (27) is unaffected by a single soft error event since the majority of the total current (23) remains steered through the correct resistive element (24 or 25).