Abstract: A method for cleaning a semiconductor processing component is provided. The process calls for directing a stream of cleaning media at a surface of the component, the cleaning media including zirconia. After cleaning with the cleaning media, frozen CO2 (dry ice) pellets may be directed at the surface to further clean the component.

Abstract: A tPEN layer (108) having a tensile stress is formed over a conductive gate stack (104-106) provided on a semiconductor substrate. Following the formation of the conductive gate stack (104-106), an anneal is performed. The conductive gate stack includes a metal layer to prevent outgassing and poly depletion during the anneal. Next, a photoresist layer (110) is formed and patterned to form a gate (122, 124).

Abstract: A method for processing a conductive layer, such as a doped polysilicon layer (14) of a gate stack, provides a degas step after precleaning to reduce particle count and defectivity. The conductive layer is provided on a substrate (10), e.g., a silicon wafer. The substrate (10) and conductive layer are subjected to an elevated temperature, under a vacuum, whereby certain species are liberated. The substrate having the conductive layer formed thereon is then removed from the chamber, and moved to a second, separate chamber, in which a second conductive layer (20) is deposited. By switching chambers, the liberated species are largely prevented from contributing to particle count at the interface between the conductive layers. Alternatively, the second conductive layer is formed in the same chamber, provided that the liberated species are removed from the chamber prior to deposition of the second conductive layer.

Abstract: A dielectric film (110) is formed overlying a semiconductor device substrate (10). A dielectric post (204) having an outer peripheral boundary having sidewalls is formed over the dielectric film (110). A first conductive film (402) is deposited at least along the sidewalls of the dielectric post (204) to form a lower electrode. A capacitor dielectric film (1801) is deposited on the first conductive film, and a upper electrode (1802) is formed on the capacitor dielectric film (1801).

Abstract: A process for carrying out chemical reactions in the gas phase or gas-liquid phase comprises feeding the chemical reagents under pressure into the combustion chamber of a turbine engine, where they react to form a desired chemical product. The heat energy evolved in the process can be utilized through the action of the turbine to power auxiliary equipment attached to the turbine engine, such as an electrical generator. In another embodiment, the turbine engine is utilized to carry out at least two reactions: a primary reaction which occurs in the combustion chamber of the engine, and a second reaction which occurs in an augmentor-section of the engine, utilizing the product of the primary reaction as a reagent in the production of a final product.

Abstract: A semiconductor device (100) including a die (110) electrically connected to a substrate (120), wherein the substrate has a novel interconnect routing structure. The routing structure has a plurality of interconnects (122) including a plurality of intermediate vias (140), including both intermediate vias associated with supply interconnects and signal interconnects, that are clustered together to reduce undesirable mutual loop inductance (L.sub.m) and reduce switching noise (.DELTA.I). A plurality of first printed wires (128a) and a plurality of second printed wires (128b) may incorporated in the substrate for routing of the plurality intermediate vias in cluster form. The substrate may have a plurality of clusters of the intermediate vias.

Abstract: A polishing system (10) is used to polish a semiconductor wafer (16) in accordance with the present invention. Polishing system (10) includes a wafer carrier (14) which includes a modulation unit (20). Modulation unit (20) includes a plurality of capacitors made up of a flexible lower plate (22) and a plurality of smaller upper plate segments (24). A controller (40) monitors the capacitance between each smaller upper plate segment (24) and lower plate (22), and compares the measured capacitance against a predefined set capacitance. To the extent the measured capacitance and predefined capacitance are different, controller (40) adjusts the voltage being applied to the respective upper plate segment (24) so that the measured capacitance and predefined capacitance are aligned. Thus, the present invention is able to achieve dynamic and localized control of the shape of the wafer as it is being polished.

Abstract: Semiconductor devices (140, 410, 610) are tested or burned-in while in a handling or shipping tray (100, 500, 700) using a test contactor (150, 450, 750, 850, 950) which engages either a cell (120, 520, 720) of the tray or the device itself during testing. A tray having a plurality of devices is moved by a handling system in an initial alignment operation where one or more devices is generally aligned beneath the test contactor. Then, the tray or the test contactor is moved in a vertical direction so that engagement features of the test contactor engage either the tray cell or the device to be tested to bring the device into final alignment for testing. Upon final alignment, contacts (152, 452, 752, 852, 952) of the test contactor physically and electrically contact leads (141, 414, 614) and in-tray testing of the devices is performed. In-tray testing reduces manufacturing cycle and minimizes device lead damage by eliminating pick and place handling of the devices at test.

Abstract: A method for forming a semiconductor device, including providing a silicon substrate (10), forming a gate stack (11) on the substrate (10), coating a deep ultra-violet (DUV) photoresist (30) on the gate stack (11), exposing and developing the photoresist (30), and etching the gate stack (11). According to the present invention, the gate stack (11) has a dielectric nitride layer (26), particularly, a silicon nitride layer. An adhesive oxide layer (28) is provided between the nitride layer (26) and the photoresist (30) to prevent undesirable lifting of the photoresist (30). Yield is greatly increased and defectivity is reduced.

Abstract: A non-destructive method of determining substrate tilt within a packaged component includes providing the packaged component (10) with a component surface (32), providing a substrate (22) in the packaged component (10) wherein the substrate (22) has a substrate surface (33), using an acoustic wave (50) to measure a distance (34) between the component surface (32) and a region on the substrate surface (33), using another acoustic wave (53) to measure another distance (35) between the component surface (32) and a different region on the substrate surface (33), and comparing the distances (34, 35) to a threshold value.

Abstract: In on form, a TEOS based spin-on-glass is made having on the order of 10% to 25% by volume of tetraethylorthosilicate, the equivalent of on the order of 0.1% to 3.0% by volume of 70% concentrated nitric acid, on the order of 60% to 90% by volume of alcohol, and the balance water. The spin-on-glass is applied to a semiconductor substrate and heated in order to densify the spin-on-glass.

Abstract: A method of decreasing resistivity in an electrically conductive layer (23) includes providing a substrate (14), using a high density plasma sputtering technique to deposit the electrically conductive layer (23) over the substrate (14), and exposing the electrically conductive layer (23) to an anneal in an ambient comprised of a plasma (21).

Abstract: A process for fabrication of a metallized interconnect structure includes the formation of an inlaid interconnect (42) overlying an aluminum layer (34). The inlaid interconnect (42) is formed within an interlevel dielectric layer that is processed to contain an interconnect channel (24) and a via opening (14) residing at the bottom of the interconnect channel (24). The aluminum layer (34) is selectively deposited to at least partially fill the via opening (14) at the bottom of an interconnect channel (24). An adhesion layer (36) is deposited to overlie the aluminum layer (34) within the via opening (14), and a second aluminum layer (38) is blanket deposited and planarized to form the inlaid interconnect (42) in the interconnect channel (24).

Abstract: A process for probing a semiconductor wafer involves bringing the bond pads (63) of a semiconductor die (114) into contact with probes (122) of a probe card (120) by moving a probe chuck (110) in the Z-direction. Initial contact is made with "zero-overdrive." The probe chuck is then moved in a small amount in the Z-direction to induce a pressure in the probe. Scrubbing of the probes against the pads is then performed by moving the probe chuck in the X and Y directions. During movement in the X and Y directions, the pressured induced in the probe is released, causing the probe to begin to break through an oxide layer (62) of the bond pad. If the oxide layer is not completely broken, the movement of the probe chuck in the Z and then X & Y directions is repeated until electrical contact between the probes and the bond pads is made.

Abstract: Solder bumps are formed on a substrate, such as a semiconductor die (28) or wafer, using a screen printing and reflow operation. Solder paste (18) is screened into openings (14) of a stencil (10). The paste is reflowed within the stencil to produce a solder preform (22). The stencil and solder preforms are then aligned over the substrate to be bumped so that the preform aligns with a metal pad (30) on the substrate. The solder preforms are again reflowed, and the solder within the openings of the stencil is drawn onto the metal pad. To facilitate the transfer of the solder from the stencil to the metal pad, a second stencil (12) can be used to form a protrusion (27) on the solder preform. The protrusion contacts the metal pad during the transfer reflow operation to facilitate removing the solder from the stencil.

Abstract: A method for determining the cleanliness of a surface of a substrate involves using a visual pattern (17, 29). The visual pattern is either provided in the optical portion of a visual system or is formed on the surface of the substrate to be analyzed. A liquid droplet (26, 27) is dispensed onto the substrate surface, and the extent of the spread area of the droplet is compared to the visual pattern. If the area of the droplet is greater than or equal to a tolerance as signified by the pattern markings, then the surface of the substrate is determined to be sufficiently clean. In relying upon a simple visual comparison of the area of the surface covered by the droplet with an empirically determined visual pattern, a method for analyzing surface cleanliness is consistent between operators and surfaces, is easy to set up and operate, and improves manufacturing throughput.

Abstract: A ball grid array semiconductor device (30) includes a plurality of conductive balls (36) and a plurality of conductive castellations (18) around its periphery as redundant electrical connections to a semiconductor die (12). During testing of the device in a test socket (50), the conductive castellations are contacted by test contacts (54). The test contacts do not come in physical contact with the conductive balls. As a result, when testing is performed at elevated temperatures near the melting point of the conductive balls, the conductive balls are not deformed by the test contacts, thereby eliminating cosmetic-defects. Additionally, the absence of physical contact between the conductive balls and the test contacts during testing reduces the likelihood that conductive balls will inadvertently fuse to the test socket or create solder build-up on the test contacts.

Abstract: An apparatus(19) for holding a testing substrate in a wafer prober (16) has a plate (34) hinged to a head stage (18) of the equipment. The plate has two concentric openings to form a ledge (35) for holding the testing substrate (10). Additionally, the ledge has two asymmetrically placed locating pins (38) to allow automatic alignment of the testing substrate which has corresponding alignment holes. A latch (36) locks the plate against the head stage to securely fix the testing substrate in place so that it can make and maintain contact with a pogo pin area (26) on the head stage. The tester also has a wafer support chuck (20) upon which a semiconductor wafer (22) is placed with its active surface up. The head stage of the tester is closed so that the testing substrate contacts the active surface of the semiconductor wafer, and electrical testing may then be performed on the semiconductor wafer.

Abstract: A semiconductor device (30) includes a bumped semiconductor die (32) having a plurality of input/output (I/O) bumps (36) and a plurality of alignment bumps (38). Alignment bumps (38) are formed at the same time as I/O bumps (36) and are used by a vision system to properly align die (32) to a mounting substrate (34) for attachment thereto. Because the alignment bumps are smaller than the I/O bumps, the alignment bumps are not damaged during manufacturing operations such as wafer probe, burn-in, or test, and therefore maintain their original shape. The vision system can thus use the alignment bumps to repeatedly and accurately align the die to the mounting substrate, thereby eliminating misalignment caused by damage to the I/O bumps.