Abstract: In a data processing system comprising a central processing unit (CPU), a memory management unit (MMU) and a storage system, the MMU translates each of the logical addresses output by the CPU to a corresponding physical address in the storage system by selectively using translation descriptors stored in an address translation cache. In response to receiving a dynamic disable signal, the MMU will provide each logical address as the corresponding physical address without translation. In addition, the MMU will preserve the state of the entries in the address translation cache, and "freeze" the translation activities.

Abstract: Adjusting field effect transistor (FET) threshold voltage (V.sub.T) by diffusing impurities in polysilicon gates through a refractory metal silicide. Dopants of different conductivities may be cross-diffused. This adjustment can be made relatively late in the fabrication of the wafers to provide a quick turn around time of custom circuits, gate arrays and application specific integrated circuits (ASICs). A masking step selectively provides blocking elements to prevent the diffusion from occurring in certain of the FETs.

Abstract: A single transistor EEPROM cell comprises a source, a channel, a drain, a floating gate and a control gate. The control gate and the floating gate are co-extensive over the channel. Programming is achieved by charge injection from the channel and erasing is achieved by tunneling to the source. An array organization is disclosed which features a source/erase control line shared between two adjacent rows of the array, providing efficient byte-at-a-time erasing. An erasure scheme is disclosed which involves repetitive erase pulse-read-erase pulse cycles together with means for assuring complete erasure while preventing over-erasure from driving any cell in the array into depletion mode.

Abstract: A process is disclosed for fabricating complementary insulated gate field effect transistors including doped field isolation regions and optional punch through protection. In one embodiment of invention, a silicon substrate is provided which has N-type and P-type surface regions. First and second masks are formed overlying active areas of the two surface regions. A third mask is then formed overlying the first region and the first mask. P-type impurities are implanted into the second region with an implant energy which is sufficient to penetrate through the second mask but insufficient to penetrate through the third mask. A second P-type implant is performed with an implant energy insufficient to penetrate through either mask. The first implant will aid in preventing punch through while the second implant dopes the field region. A fourth mask is then formed overlying the second region and the second mask.

Abstract: An input buffer which can be used as a TTL to CMOS input buffer in a CMOS integrated circuit has a CMOS input inverter for receiving an external input signal. The typical threshold voltage of the P and N channel transistors is relatively low for high speed operation. At least one of the P and N channel transistors of the input inverter has the magnitude of its threshold voltage increased by applying appropriate back bias voltage in the well in which it resides.

Abstract: A TTL to CMOS input buffer has a CMOS inverter for receiving the TTL signal on its input. The inverter has a P channel transistor coupled between VDD and the output of the inverter, which has relatively low gain so that there is very little current flow through the inverter when the TTL signal is at low voltage logic high. A switch is coupled between VDD and the output of the inverter. The switch couples VDD to the output of the inverter in response to the TTL signal switching from a logic high to a logic low.

Abstract: An envelope detector comprising an absolute value detection portion and a filter portion implemented in switched capacitor technology with common circuit elements is provided. The absolute value of an input signal is obtained and an amplitude envelope is filtered therefrom. The absolute value detection portions and the filter portions share the same integrating operational amplifier to perform the envelope detection.

Abstract: A typical feature of a data processor is a bounds check. A bounds check is achieved when a determination is made as to whether a check value, typically an address or datum, is within predetermined bounds. Such check values may be signed or unsigned. By requiring that the upper bound be numerically larger than the lower bound for doing a signed check, and requiring that the upper bound be logically larger than the lower bound for doing an unsigned check, the bounds check is performed by the data processor without the need of receiving a signal which informs the data processor in advance as to whether the check is to be signed or unsigned.

Abstract: A static CMOS delayed flip-flop uses only a weak P channel transistor for reinforcing a logic high at a control node while using a pair of series connected N channel transistors for reinforcing a logic low at the control node. Only a single P channel device is required because it can be made to have sufficiently low gain at a relatively small device size so that the control node can have it logic state switched by an N channel device of comparable size.

Abstract: A minimum design I.sup.2 L full adder with carry look ahead capabilities has all arithmetic logic unit functions, including OR, AND, XOR and SUM generated within. The full adder is easily extended to an arithmetic logic unit where all logic functions are selected at the output.