Abstract: A pulse train generator comprising a shift register with feedback for proing an output pulse for every m clock pulses applied to the shift register stages. The feedback shift register normally has a maximal length 2.sup.n -1, where n is the number of stages. Clock pulses are applied to the shift register until an all-ONE condition is reached; thereupon, (m-1) additional clock pulses are applied and the states of the register stages can then be sensed. False count correction is obtained by the combination of a detector and an analog integrator.