Abstract: A method of manufacturing a liner insulating layer for a node contact hole. A substrate having an first insulating layer formed thereon is provided, wherein the first insulating layer has a node contact hole penetrating through the first insulating layer and exposing the substrate. A protective layer is formed on the substrate exposed by the node contact hole. A liner insulating layer is formed on the first insulating layer and in the node contact hole. A second insulating layer is formed on a portion of the liner insulating layer formed on the sidewall of the node contact hole. A portion of the liner insulating layer uncovered by the second insulating layer is removed. The protective layer and the second insulating layer are removed.

Abstract: A method of fabricating a flash memory. After the formation of a trench isolation structure, openings are formed, in a direction perpendicular to the orientation of the trench isolation structure, in order to form a buried bit line. A spacer is formed on the opening sidewall of the bit line in which the distance between a top of the spacer and the interface of a substrate and a pad oxide layer is the depth of the source/drain region. The opening is then filled with a doped polysilicon conducting layer used as the buried bit line. The dopant from the polysilicon conducting layer is driven into the substrate to form the source/drain region.

Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor on a semiconductor substrate is described. The invention introduces an air chamber with a low dielectric constant between the gate and the source/drain region so as to lower the fringing electric field between the gate and the source/drain region. Moreover, the dielectric constant of the dielectric layer between the gate and the source/drain region is reduced. Therefore, the gate-to-drain capacitance is decreased in the MOS transistor.

Abstract: A method for manufacturing a dual-cylinder bottom electrode. Because the node contact hole is formed by self-aligned etching and the materials of the spacers are conductive materials, the node contact hole is smaller than the resolution of the photolithography. Hence, the size of the device can be greatly reduced. Furthermore, because of the dual-cylinder bottom electrode, the surface area of the bottom electrode is enlarged in a limited space. Therefore, the capacitance of the capacitor is increased.

Abstract: In this method for manufacturing a split-gate flash memory cell, a floating gate and a control gate are formed over a substrate, and then first spacers are formed on the sidewalls of the gate structure. Next, a polysilicon layer is deposited over the gate structure and the substrate, and second spacers are formed on the sidewalls of the polysilicon layer. A self-aligned ion implantation process is performed, using the second spacers as a mask, implanting ions into the semiconductor substrate to form a drain region. This maintains the channel length. After removing the second spacers, another ion implantation process is performed to create a source region in the semiconductor substrate. During the second implantation, the polysilicon layer offers some protection for the semiconductor substrate, maintaining the capacity for tunneling. Finally, a conductive layer is formed over the polysilicon layer, and the conductive layer combined with the polysilicon layer forms the select gate.

Abstract: A method of fabricating a high power bipolar junction transistor. A P-type substrate having an N-type buried region is provided and a trench is formed within the substrate to expose the buried region. N-type ions are implanted and driven into the sidewall of the trench to form a sinker. Since the area and the depth of implantation are larger and deeper than that in prior art, the concentration of the sinker is more uniform and the diffusion range is easily controlled. An N-type epitaxial layer is then formed in the trench and an emitter, a base and their contacts are formed by conventional technique.

Abstract: A crow-bar current reduction circuit for use with a NMOS output circuit a gate voltage control circuit (GVC). The GVC receives a data signal and an output enable signal and generates control signals to drive the gates of the output transistors of the output circuit. When enabled, the GVC delays the rising edges of the gate control signals so as to help ensure that during a transition of the output signal generated by the output circuit, the NFET that was conductive before the transition is "turned off" to become non-conductive before the NFET that was non-conductive before the transition is "turned on" to become conductive. When adapted for a CMOS output circuit, the GVC delays the rising edge of the gate control signal provided to the NMOS pull-down transistor and delays the falling edge of gate control signal provided to the PMOS pull-up transistor.

Abstract: A method for fabricating a transistor with a borderless contact is provided. The method contains forming several dummy gates on a substrate. Each dummy gate includes a pad oxide layer and a dummy gate layer. A doped polysilicon layer is formed on the substrate at each side of the dummy gates. A shallow trench isolation (STI) is formed to define active regions. A horizontal gate opening is formed to expose two adjacent dummy gates. The dummy gate layer is removed to expose sidewalls of the doped polysilicon. Spacers are formed on the exposed sidewalls of the doped polysilicon layer. A threshold voltage doped region and an anti-punch-through doped region are formed in the substrate by ion implantation, using the doped polysilicon layer and the spacers as a mask. The exposed pas oxide layer is removed and a gate oxide layer is formed instead. A gate metal layer is formed on the gate oxide layer between the spacers, in which the horizontal gate opening is also filled.

Abstract: The present invention provides a fabricating method of a high-voltage device. The invention provides N.sup.-- -type doped regions with properly low doping concentration in order to increase breakdown voltage. Field oxide layers are used as masks in a self-aligned ion implantation step to form N.sup.- -type doped drift regions with a higher doping concentration than the N.sup.-- -type doped regions. A recessed gate is formed so that the channel length is increased and the curvature of the electrical distribution lines on the edge of a drain region nearby a channel is decreased while the device is operated under high voltage.

Abstract: A gas tube with heating apparatus. The gas tube is applicable in a chemical vapor deposition machine. The gas comprises a gas circulating tube and a coaxial gas tube invaginating a gas transporting tube therein. A heater is installed in the gas circulating tube, while the coaxial tube is covered by a thermal insulating layer. In addition, a control valve, a pressure gauge, and a particle trap are installed in a gas supplying tube connecting with the gas circulating tube.

Abstract: A voltage boosting circuit having an asymmetric MOS in DRAM. A gate of a first NMOS connects to a voltage source, and a source region of the first NMOS connects to a row decoder. A gate of the asymmetric NMOS connects to a drain region of the first NMOS. A drain region of the asymmetric NMOS connects to a column decoder, and a source region of the first asymmetric NMOS connects to a word line. A gate of a second NMOS connects to the column decoder, a source region of the second NMOS connects to a ground terminal and a drain region of the second NMOS connects to a source region of the first asymmetric NMOS.

Abstract: A metal-line structure in an integrated circuit (IC) and a method of fabricating the same are provided. The metal-line structure includes a barrier layer formed at a selected location over the dielectric layer, a metallization layer formed over the barrier layer, an ARC formed over the metallization layer, and a spacer structure formed over all the exposed sidewalls of the barrier layer, the metallization layer, and the ARC. The forming of the spacer structure on each of the metal lines can help prevent the occurrence of extrusions along the sidewalls of the metal lines in the IC device that would otherwise cause dielectric cracks and thus lead to undesired bridging between neighboring metal lines as in the prior art. Moreover, the method of fabricating such a metal-line structure can be carried out without having to perform photolithography, thus reducing manufacturing cost.

Abstract: The method of the invention starts with forming a mask on a blank wafer, wherein the mask contains a number of openings that expose a portion of the wafer. By performing a wet oxidation process, field oxide is formed on the exposed surface of the wafer. The wafer surface is then become ragged after the mask and the field oxide are removed. In order to further increase the surface area of a dummy wafer, an etching process is performed on the ragged surface after a hemispherical grained layer is formed on the ragged surface.

Abstract: A method of forming a layer of hemispherical grain polysilicon over the lower electrode of a capacitor. The method comprises the steps of providing a substrate that has a field effect transistor already formed thereon, and then forming an insulating layer with a contact opening over the substrate. Subsequently, a polysilicon layer is formed over the insulating layer that completely fills the contact opening. This polysilicon layer is electrically coupled to one of the source/drain regions of the field effect transistor. Thereafter, a thin buffer layer is formed over the polysilicon layer, and then the thin buffer layer is patterned. The thin buffer layer is used as a mask for covering the polysilicon layer that is to be part of the lower electrode of a capacitor. Next, a plasma etching operation is carried out to remove the thin buffer layer and a portion of the polysilicon layer at the same time.

Abstract: A device and method for digitizing a RSSI signal in a wireless transmission system is disclosed, which comprises a micro-controller having a ring counter and a controller, a low-pass filter, and a comparator. To start a digitization process, the controller gradually increases a numeric control signal to control a ring counter to generate a square wave with different duty cycle. Subsequently, the square wave is filtered by a low-pass filter to obtain a DC threshold voltage. If the threshold voltage is larger than the RSSI voltage, the digitization process is complete and the final numeric control signal represents the digitized RSSI signal.

Abstract: A chemical-mechanical polishing station comprises a polishing table that has concentric rings. The rings are separated from each other by a small gap and all rings are capable of rotating in the same prescribed direction. A polishing pad is mounted on top of each ring, and a delivery tube is positioned at a distance above the polishing pads. The delivery tube further includes a tube handle and a tube surface, and the tube surface has a plurality of holes drilled in it for delivering slurry to the polishing pad surface. Each concentric ring of the polishing table is able to rotate such that all the rings have the same tangential polishing speed. Therefore a wafer surface can be more uniformly polished. Moreover, material having different density, roughness and chemical composition can be chosen to fabricate the polishing pads so that an even better polishing result can be obtained.

Abstract: A method of forming landing pads for a bit line and a node contact is provided. First, a first dielectric layer is formed on a substrate having a transistor structure thereon. The first dielectric layer is defined and etched in a self-aligned process to form a contact opening to the substrate. A second dielectric layer is formed on the first dielectric layer and is etched back to form a spacer on the opening sidewall. Then, a conductive layer is formed on the first dielectric layer and fills the opening. A bit line is formed by partially removing the conductive layer through a photo-resist mask provided on the conductive layer, wherein the conductive layer filling the opening is left to form a landing pad.

Abstract: A programmable frequency following device is provided. The programmable frequency following device includes a frequency divider for dividing the input frequency by a predetermined divisor. A frequency counter is used to count the output frequency of the programmable frequency following device, the frequency counter being reset to 0 after reaching a cycle time of the output frequency from the frequency divider. A programmable frequency comparator is used to compare the output count from the frequency counter with a user-programmable reference value at the time before the frequency counter is reset to 0. An up-down counter is under control by the programmable frequency comparator to count either in the upward or downward direction, and the count is locked when the output frequency reaches an intended value.

Abstract: A method of fabricating a DRAM. A substrate comprising a MOS is provided. A first dielectric layer is formed on the substrate. The first dielectric layer is patterned to form a bit line contact window exposing a source region of the MOS and a node contact window exposing a drain region of the drain region simultaneously. The bit line window and the node contact window are filled with a bit line and a polysilicon plug by the formation of the same polysilicon layer, respectively. A second dielectric layer with an opening exposing the polysilicon plug is formed on the first dielectric layer. The sidewall and bottom surface of the opening are covered by another polysilicon layer. The second dielectric layer is removed to leave a node contact in contact with the polysilicon plug.

Abstract: A timing circuit can be selectively configured to generate output pulses in response to either the falling edges or the rising edges of an input signal. The timing circuit includes a multiplexer, an output pulse width controller (OPWC), a gating circuit (GC) and a latch circuit. The OPWC includes a delay circuit that can be configured to provide a predetermined delay .delta. that can be larger than the pulse width of the input signal pulses. The multiplexer is connected to receive a first input signal and an inverted version of a second input signal. The first input signal is used in a rising edge triggered mode, whereas the second input signal is used in a falling edge triggered mode. The multiplexer receives a mode signal to selectively output one of the input signals to the GC. The GC is also connected to receive the output signal from the OPWC.