Abstract: A digital-to-analog converter (DAC) includes a mismatch shaping feedback vector quantizer configured to store state information in expanded format using One-Hot Encoding of a matrix. The expanded state format storage enables implementation of a simplified state sorter for the vector feedback mechanism of the vector quantizer. The simplified state sorter may minimize the variance of ones (or other symbols representing state values) in the matrix, and allow performing sorting in a reduced number of clock cycles. For example, sorting may be performed on a predetermined edge of single clock cycle, or on two edges of the same clock cycle. The matrix may be normalized periodically or as needed, to avoid overflow and underflow. The DAC may be used as a quantizer of a modulator of an access terminal in a cellular communication system.

Abstract: A time-to-digital converter (TDC) with fine resolution of less than one inverter delay is described. In an exemplary design, the TDC includes first and second delay paths, a delay unit, and a phase computation unit. The first delay path receives a first input signal and a first reference signal and provides a first output. The second delay path receives a second input signal and a second reference signal and provides a second output. The delay unit delays the second input signal relative to the first input signal or delays the second reference signal relative to the first reference signal, e.g., by one half inverter delay. The phase computation unit receives the first and second outputs and provides a phase difference between the input signal and the reference signal. Calibration may be performed to obtain accurate timing for the first and second delay paths.

Abstract: Techniques for detecting and mitigating interference are described. A device (e.g., a cellular phone) senses interference levels and digitally reconstructs the expected interference in the received signal. The device may correlate the reconstructed interference with the received signal and determine interference in the received signal based on correlation results. The device may adjust the operation of one or more circuit blocks (e.g., a mixer, an LNA, etc.) in a receiver based on the detected interference in the received signal. Alternatively or additionally, the device may condition the digital interference to obtain conditioned reconstructed interference matching the interference in the received signal and may then subtract the conditioned interference from the received signal.

Abstract: Techniques for cancelling a disturbance signal from a PLL output signal. In an aspect, a cancellation signal is combined with the signal input to a VCO or DCO in the PLL. In a further aspect, the appropriate cancellation signal is derived by analyzing one or more signals within the PLL. The signals within the PLL may be correlated against one or more disturbance signal templates, such as a sinusoid having a known frequency, to derive one or more correlation coefficients. The coefficients may be applied to weight one or more disturbance synthesis functions to generate the cancellation signal. Further aspects provide for joint analysis, synthesis, and cancellation of signals having unknown frequency from the PLL output.

Abstract: A phase locked loop apparatus includes an oscillator, a variable capacitance device, a selectable capacitance device, and a capacitance controller that is configured to provide a control signal to the selectable capacitance device. The selectable capacitance device is connected to the oscillator and is responsive to the control signal such that the selectable capacitance device has a first capacitance at a first control signal value and a second capacitance at a second control signal value. The capacitance controller only selects either the first capacitance or the second capacitance by providing a control signal that has the first control signal value to select the first capacitance and having the second control signal value to select the second capacitance.

Abstract: A Delay-Locked Loop (DLL) uses a delay line to delay a first signal by a “delay time”, thereby generating a second signal. A capacitor is charged at a first rate starting at a first edge of first signal and continuing until an edge of the second signal. The capacitor is then discharged at a second rate until another edge of the first signal. A control loop controls the delay time such that the amount the capacitor is charged is the same as the amount the capacitor is discharged. The delay time is constant and is substantially independent of variations in the duty cycle of the first signal. In one example, duty cycle distortion cancellation is accomplished by changing the first rate proportionally with respect to changes in first signal duty cycle. In another example, the first and second rates are independent of the duty cycle of the first signal.

Abstract: A digital phase-locked loop (DPLL) supporting two-point modulation is described. In one design, the DPLL includes a phase-to-digital converter and a loop filter operating in a loop, a first processing unit for a lowpass modulation path, and a second processing unit for a highpass modulation path. The first processing unit receives an input modulating signal and provides a first modulating signal to a first point inside the loop after the phase-to-digital converter and prior to the loop filter. The second processing unit receives the input modulating signal and provides a second modulating signal to a second point inside the loop after the loop filter. The first processing unit may include an accumulator that accumulates the input modulating signal to convert frequency to phase. The second processing unit may include a scaling unit that scales the input modulating signal with a variable gain.

Abstract: A controllable filter arrangement with a voltage controlled device that subjects a signal to a predetermined impedance as part of the filtering process when the voltage controlled device is in an active state. In an inactive state, the voltage controlled device may subject the signal to an impedance that prevents all frequencies of the signal from passing. This configuration may advantageously increase frequency selectivity and reduce insertion loss, size, cost, and tuning complexity when compared with conventional filter designs.

Abstract: A latch includes three circuits. The first circuit drives a first output (QB) to a first level when a first input (D) and a first clock phase (CK) are both low, to a second level when D and CK are both high, and provides high impedance (HI-Z) when different logic levels are applied to D and CK. The second circuit drives a second output (Q) to the first level when a third input (DB) and a complimentary clock phase (CKB) are both low, to the second level when DB and CKB are both high, and provides HI-Z when different logic levels are applied to DB and CKB. The third circuit maintains voltages of Q and QB when the first and second circuits provide HI-Z at Q and QB. Odd-number dividers constructed with such latches produce 50% duty cycle operation without restricting output pulse widths to integer multiples of input periods.

Abstract: A wideband frequency generator has two or more oscillators for different frequency bands, disposed on the same die within a flip chip package. Coupling between inductors of the two oscillators is reduced by placing one inductor on the die and the other inductor on the package, separating the inductors by a solder bump diameter. The loosely coupled inductors allow manipulation of the LC tank circuit of one of the oscillators to increase the bandwidth of the other oscillator, and vice versa. Preventing undesirable mode of oscillation in one of the oscillators may be achieved by loading the LC tank circuit of the other oscillator with a large capacitance, such as the entire capacitance of the coarse tuning bank of the other oscillator. Preventing the undesirable mode may also be achieved by decreasing the quality factor of the other oscillator's LC tank and thereby increasing the losses in the tank circuit.

Abstract: A method for self testing a multiband voltage controlled oscillator (VCO) is described. A first frequency band in a VCO is selected. An N value is selected for a frequency divider that produces a tuning voltage for the VCO that is between a low tuning voltage limit and a high tuning voltage limit for the VCO. The N value is adjusted in one direction until the tuning voltage reaches one of the tuning voltage limits. This N value at the tuning voltage is a first limit value. The frequency bands are switched from the first frequency band to a second frequency band that is adjacent to the first frequency band.

Abstract: A high speed flexible interconnect cable for an electronic assembly includes a number of conductive layers and a number of dielectric layers. Conductive signal traces, located on the conductive layers, combine with the dielectric layers to form one or more high speed electrical transmission line structures. The cable can be coupled to electronic components using a variety of connection techniques. The cable can also be terminated with any number of known or standardized connector packages.

Abstract: A cascode amplifier with protection circuitry is described. In one exemplary design, the amplifier includes multiple branches coupled in parallel, with at least one branch being switchable between “on” and “off” states. Each switchable branch includes a gain transistor coupled to a cascode transistor. The gain transistor amplifies an input signal and provides an amplified signal in the on state and does not amplify the input signal in the off state. The cascode transistor buffers the amplified signal and provides an output signal in the on state. The output signal swing may be split between the gain transistor and the cascode transistor in both the on and off states with the protection circuitry. Each transistor may then observe a fraction of the voltage swing. The voltage splitting in the off state may be achieved by floating the gain transistor and shorting the gate and source of the cascode transistor.

Abstract: An oscillator includes a resonator, a first and a second p-type transistor, and a first and a second n-type transistor. The resonator has a first terminal and a second terminal. The first p-type transistor is switchably connected to the first terminal while the second p-type transistor is switchably connected to the second terminal. A first drain of the first n-type transistor and the second drain of the second n-type transistor are electrically connected to the first terminal and the second terminal, respectively. The oscillator is capable of operating in an NMOS only mode and in a CMOS mode.

Abstract: An integrated circuit incorporating a bias circuit for a current-controlled oscillator (ICO) with improved power supply rejection ratio (PSRR) is described. The bias circuit for the ICO includes two error amplifiers. The first error amplifier regulates the bias voltage, VBN, referenced to a ground supply (GND). The second error amplifier regulates the bias voltage, VBP, referenced to a positive power supply (VDD). The VBP and VBN bias voltages have improved PSRR relative to conventional ICO bias circuits for noise injected into VDD and GND.

Abstract: A power controller having good transient performance and including a voltage regulator and one or more (K) transient recovery circuits is described. The voltage regulator receives a supply voltage and generates a regulator output signal used to generate K output voltages for K loads. Each transient recovery circuit detects for transients in a respective output voltage and corrects the detected transients. In one design, the transient recovery circuit compares the output voltage against a low threshold voltage, detects a low transient when the output voltage is below the low threshold voltage, and couples the output voltage to a high voltage to correct the low transient. Alternatively or additionally, the transient recovery circuit compares the output voltage against a high threshold voltage, detects a high transient when the output voltage is above the high threshold voltage, and couples the output voltage to a low voltage to correct the high transient.

Abstract: A low-voltage level converter provides level conversion for multiple-supply voltages for very large scale integration (VLSI) systems. Low voltage-level down conversion is achieved at very low voltage operation for on-chip test circuitry for multiple-supply voltage systems. The converter includes an output driver PMOS FET (positive metal-oxide semiconductor field effect transistor) with its well grounded. An output NMOS FET (negative MOS FET) and an extra input pulldown NMOS FET are connected in parallel to the input of the converter. The extra input pulldown NMOS FET provides a negative gate voltage at its drain to the output driver PMOS FET gate. The negative gate voltage and grounded well significantly decrease rise time of the output signal noise pulse of the converter and virtually eliminate a negative spike voltage at the initial transition of the output pulse produced by coupling effect between the input pulse and output pulse due to Miller capacitance effect.

Abstract: A circuit receives a first signal (for example, a baseband signal) and mixes it with a local oscillator (LO) signal, and outputs a second signal (for example, an RFOUT signal). The circuit includes multiple identical Mixer and Frequency Divider Pair (MFDP) circuits. Each MFDP can be enabled separately. Each MFDP includes a mixer and a frequency divider that provides the mixer with a local version of the LO signal. The MFDP outputs are coupled together so that the output power of the second signal (RFOUT) is the combined output powers of the various MFDPs. By controlling the number of enabled MFDPs, the output power of the second signal is controlled. Because the MFDPs all have identical layouts, accuracy of output power step size is improved. Because LO signal power within the circuit automatically changes in proportion to the number of enabled MFDPs, local oscillator leakage problems are avoided.

Abstract: Techniques for designing a high performance analog switch for use in electronic circuit applications. In one aspect, a variable bulk voltage generation module is provided to vary the bulk voltage of a transistor in the switch, such that the threshold voltage of the transistor is reduced during the on state. In another aspect, a pulling transistor is provided to pull a middle node of the switch to a DC voltage during the off state to further increase the isolation provided by the switch.

Abstract: Techniques for adaptively control of a loop filter sampling interval to mitigate the effects of charge pump leakage current in an apparatus including a phase lock loop circuit are provided. In one aspect, the apparatus includes a voltage controlled oscillator (VCO), a phase frequency detector (PFD) providing a phase comparison operation, a loop filter providing a control voltage to lock the VCO to a desired operating frequency, and a charge pump configured to provide an output signal to the loop filter in response to at least one of an UP pulse and a DOWN pulse. The apparatus further includes a sampling switch, coupled between an input of the loop filter, an output of the charge pump, and characterized by a sampling interval.