Abstract: Embodiments that make DFM alterations to cells of 1×N building blocks via a closed-loop 1×N compiler are disclosed. Some embodiments comprise using a 1×N compiler to detect a relationship between two adjacent cells of a 1×N building block. Based on the relationship, the embodiments select a DFM alteration and apply the alteration to a physical design representation. The embodiments may apply various types of DFM alterations depending on the relationship, such as adding polysilicon, adding metal to create redundant connections, and merging diffusion areas to increase capacitance on supply nodes. Further embodiments comprise an apparatus having a cell examiner to examine two adjacent cells of a 1×N building block and determine a relationship of the two cells. The apparatus also comprises a DFM selector to select a DFM alteration based on the relationship and a DFM applicator to apply the selected DFM alteration to one of the cells.

Abstract: Embodiments that reassemble hierarchical representations in a closed-loop 1×N system are disclosed. Some embodiments comprise creating a flat netlist from a hierarchical representation of a 1×N building block, creating attributes for the flat netlist, and altering one or more elements of the flat netlist, such as by an operation of a logic design tool, a synthesis tool, a physical design tool, or a timing analysis tool. The embodiments further comprise generating a second hierarchical representation of the 1×N building block that reflects the altered element. Further embodiments comprise an apparatus having a 1×N compiler and a reassembler. The 1×N compiler may create attributes for a flat netlist of elements of a hierarchical representation of a 1×N building block. The reassembler may use the attributes to create a second hierarchical representation of the 1×N building block that reflects alteration of elements to the flat netlist.

Abstract: A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure.

Abstract: In an NXN switch a plurality of buses interconnect the individual input modules to all of the output modules in a predetermined sequence. The input modules store the received cells and a unique ID. When selected the input module places a cell and its ID on selected ones of the buses along with a multicast vector which identities which of the output modules is to process the cell on a bus. The output modules examine the multicast vector and process the cell (table lookup) if selected In the multicast vector. If an output module is unable to process a required cell (successful table lockup) it sets a retry vector resident on the bus and the input module modifies the multicast vector to indicate only those output module(s) which failed to process a required cell. The cell, the ID and the modified multicast vector are placed on a bus in a subsequent selection of that input module.

Abstract: An electrical machine, such as a computer, network interconnecting device, etc., has an enclosure fabricated from a one piece material fold and cut into a desired form including sidewalls with an opening in one of the sidewalls and projections to which other components are connected. The components include a support member and brackets interconnecting the support member to the projections. The support and brackets are arranged to form cavities in which circuit cards can be inserted.