Patents Represented by Attorney, Agent or Law Firm Joel E. Lutzker
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Patent number: 6582075Abstract: An eyeglass assembly having a lens frame; a temple piece; an electrical insert projecting from either the lens frame or the temple piece; and a receiver provided in or on the other of the lens frame or temple piece. The electrical insert is removably insertable into the receiver for both releasably attaching the temple piece to the lens frame and for establishing an electrical connection therebetween.Type: GrantFiled: October 18, 2001Date of Patent: June 24, 2003Assignee: QR Spex, Inc.Inventors: Gregg T. Swab, Mikal Barry Greaves
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Patent number: 6565334Abstract: A counter-rotating axial flow fan for cooling electronic components comprising two or more impellers with narrow chord blades. At least one impeller rotates in a first direction and at least one impeller rotates in a second direction opposite to the first direction. The blades of the impellers are configured so as to cause air to flow in the same axial direction. The air flow generated by this counter-rotating fan is substantially greater than the air flow of an otherwise identical co-rotating fan.Type: GrantFiled: July 23, 2001Date of Patent: May 20, 2003Inventors: Phillip James Bradbury, Phep Xuan Nguyen, Chalmers R. Jenkins, Scott H. Frankel
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Patent number: 6559698Abstract: To restrain cycle-to-cycle jitter in a clock generator subjected to EMI a 2nd order PLL having a loop filter including a first capacitor and a first resistor, is provided where a reduction in a comparison frequency is avoided by using a clock modulating circuit. The clock modulation circuit is controlled by an intermediary signal provided by dividing an oscillation signal of a voltage controlled oscillator. The output of the clock modulation circuit is used to recurrently control a divider for dividing the output of the voltage controlled oscillator. Generation of high frequency noise is minimized by using a 1st order &Dgr;&Sgr; modulator(21) in the clock modulation circuit. The system behaves like a 3rd order PLL due to the presence of a second capacitor having a capacitance value of about {fraction (1/10)} or more than that of the first capacitor. The second capacitor is placed in parallel with the loop filter to restrain the cycle-to-cycle jitter by effectively removing the high frequency noise.Type: GrantFiled: October 17, 2000Date of Patent: May 6, 2003Assignee: Nippon Precision Circuits, Inc.Inventor: Satoru Miyabe
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Patent number: 6556094Abstract: An oscillator circuit adapted for a piezoelectric oscillator which has a weak oscillation output for generating high frequencies is provided. The speed of operation of the oscillator circuit is increased. An integrated circuit for such an oscillator circuit is also provided. The oscillator circuit has an amplifier portion consisting of CMOS inverters connected in cascade. MOS transistors forming the CMOS inverters have channel widths that decrease successively from the first stage to the last stage to improve the amplification factor of the amplifier portion at high frequencies. This makes it possible to amplify weak oscillation output from the quartz oscillator (XL). A filter circuit produces a peak of negative resistance at a frequency higher than conventional. This permit oscillation operation at higher frequencies.Type: GrantFiled: October 26, 2001Date of Patent: April 29, 2003Assignee: Nippon Precision Circuits Inc.Inventors: Eiichi Hasegawa, Masahisa Kimura, Kazuhisa Oyama, Kunihiko Tsukagoshi
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Patent number: 6549959Abstract: A method and computer for executing the method. A CPU is programmed to execute first and second processes, the first process programmed to generate a second representation in a computer memory of information of the second process stored in the memory in a first representation. A main memory divided into pages for management by a virtual memory manager that uses a table stored in the memory.Type: GrantFiled: November 4, 1999Date of Patent: April 15, 2003Assignee: ATI International SrlInventors: John S. Yates, David L. Reese, Korbin S. Van Dyke
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Patent number: 6515522Abstract: A drive circuit capable of adjusting a capacitive load operation, for example, respective brightness of an electroluminescence (EL) element. The drive circuit is a constant current drive system and causes a plurality of capacitive loads, for example, EL elements, to emit light. This is done by setting a coil drive signal applied to the gate of a transistor Tr1. The transistor generates a surge pulse by intermittently connecting a direct current power source to a coil L1 of a step-up circuit 1. The coil drive signal is set to a frequency in accordance with an EL element as a capacitive load driven alone or a combination of EL elements simultaneously driven. Power generated by the step-up circuit 1 can be selected, brightness of a driven EL element E1 or E2 can individually be set or brightness of the EL elements E1 and E2 simultaneously driven can be set.Type: GrantFiled: May 25, 2001Date of Patent: February 4, 2003Assignee: Nippon Precision Circuits, Inc.Inventors: Yoshiaki Inada, Masaaki Shibasaki
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Patent number: 6505025Abstract: A color image forming apparatus for printing color images for a plurality of recording mediums having one or more photoreceptors for forming toner images of different color toners. The toner images are superimposed onto the intermediate transfer drum having a length of circumference such that a plurality of color images for the plurality of recording mediums can be held on this intermediate transfer drum. The superimposition of colors is done by consecutively repeating the primary transfer of each toner developed on the photoreceptor to the intermediate transfer drum. The toner images are formed on the photoreceptor and transferred to the intermediate transfer drum consecutively if the color images to be printed are solely of a specific monochrome color.Type: GrantFiled: June 22, 2001Date of Patent: January 7, 2003Assignee: Kyocera CorporationInventor: Hiroaki Miyamura
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Patent number: 6476552Abstract: The difference of luminance between a front surface side and a rear surface side as viewed from the front surface side is reduced in a multi-layered EL lamp. An EL lamp includes a first laminate formed by serially laminating a first transparent electrode, a first luminescent layer and a first insulating layer, a second laminate formed by serially laminating a second transparent electrode, a second luminescent layer and a second insulating layer on the first laminate, and a rear electrode formed on the second laminate, wherein a dielectric constant between the first and second transparent electrodes is set to a value smaller than a dielectric constant between the second transparent electrode and the rear electrode.Type: GrantFiled: April 13, 2000Date of Patent: November 5, 2002Assignee: Seiko Precision, IncInventor: Koji Yoneda
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Patent number: 6472816Abstract: The quality of an electroluminescent module is improved, and the production costs for it are reduced. In an electroluminescent module comprising a circuit board 1 and an electroluminescent element 2 as bonded to each other, the bonding electrode parts 3a, 3b via which the two 1 and 2 are bonded, are positioned in the facing opposite sides of the electroluminescent element 2, and the two are electrically connected and physically bonded via those parts 3a, 3b to thereby reduce the bonding space. Flexible, insulating resin layers 10a, 10b are provided between the transparent electrode layer 4a and the conductive layer 11 at the connecting electrode part 3a as electrically connected with the transparent electrode layer 4a and between the transparent electrode layer 4a and the back electrode layer 7 at the connecting electrode part 3b as electrically connected with the back electrode layer 7, respectively.Type: GrantFiled: March 12, 1999Date of Patent: October 29, 2002Assignee: Seiko Precision, IncInventors: Hidetsugu Ikeda, Yoshikatsu Dobuchi
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Patent number: 6469564Abstract: A circuit simulating the function of a diode in the sense that it conducts current in one direction and blocks current in the opposite direction, but which has a low forward voltage drop. A voltage comparator and a three terminal switch are connected so that the intrinsic reverse diode associated with the switch is harnessed to conduct current in the direction in which it is desired to conduct current and to block current in the direction in which it is desired to block current. A voltage comparator controls the control terminal of the three terminal switch to turn on the switch to conduct current and to interrupt current. Alternate embodiments of voltage comparators are disclosed. The voltage comparator may include charging and discharging transistors so that the switch turns on and off at a high speed. The invention further includes a method of conducting current in one direction and blocking current in a second direction which reduces power losses.Type: GrantFiled: May 9, 2000Date of Patent: October 22, 2002Assignee: Minebea Co., Ltd.Inventor: Arian M. Jansen
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Patent number: 6457953Abstract: An axial flow fan for cooling electronic components comprising a plurality of blades for cooling electronic components wherein the blades comprise a plurality of specially designed airfoil sections, each section having along substantially the entire length thereof, a cross-sectional shape characterized by a maximum thickness located substantially constantly between about 16% chord to about 23% chord and a maximum camber located substantially constantly between about 40% chord to about 51% chord. The circuitry, housing, and blades are designed so that the axial width of the axial fan is decreased while maintaining performance parameters and design constraints.Type: GrantFiled: July 24, 2000Date of Patent: October 1, 2002Assignee: NMB (USA) Inc.Inventors: Phillip James Bradbury, Phep Xuan Nguyen, Chalmers R. Jenkins, Jr.
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Patent number: 6411172Abstract: There is disclosed an oscillator circuit in which the first capacitor is connected between the input side of a CMOS inverter in a quartz oscillator circuit and a higher potential side, the second load capacitor is connected between the input side of the inverter and a lower potential side, the third load capacitor is connected between the output side of the inverter and the higher potential side, and the fourth load capacitor is connected between the output side of the inverter and the lower potential side, so that variation in amplitudes of the voltage sources synchronized with the oscillation can be reduced with the realization of lower current consumption. There is also disclosed an oscillator circuit of reduced circuit scale. A CMOS inverter for producing oscillations, an AC coupling capacitor, and a buffer circuit are formed on one chip. A protective circuit that has been heretofore required at the input terminal portion of the buffer circuit can be dispensed with.Type: GrantFiled: January 3, 2001Date of Patent: June 25, 2002Assignee: Nippon Precision Circuits, Inc.Inventors: Kunihiko Tsukagoshi, Satoru Miyabe, Kazuhisa Oyama
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Patent number: 6411803Abstract: A information fulfillment system and method for providing information to a caller having a wireless communication device. Upon receipt of sensory prompting and manual or automatic input of access codes to the wireless communication device, the caller's identity and the input access code are verified. Thereafter, the call is connected through the PWN and along the PSTN to the system messaging or fulfillment center for automatic or live-operator delivery of the requested information. Automatic verification, connection, and billing modification processes are provided for implementation of the system and method.Type: GrantFiled: October 18, 1999Date of Patent: June 25, 2002Assignee: Ewireless, Inc.Inventors: James E. Malackowski, Kristi L. Stathis
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Patent number: 6397057Abstract: A information fulfillment system and method for providing information to a caller having a wireless communication device. Upon receipt of sensory prompting and manual or automatic input of access codes to the wireless communication device, the caller's identity and the input access code are verified. Thereafter, the call is connected through the PWN and along the PSTN to the system messaging or fulfillment center for automatic or live-operator delivery of the requested information. Automatic verification, connection, and billing modification processes are provided for implementation of the system and method.Type: GrantFiled: December 24, 1997Date of Patent: May 28, 2002Assignee: Ewireless, Inc.Inventors: James E. Malackowski, Kristi L. Stathis
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Patent number: 6360657Abstract: A printer is capable of stably feeding even a thin recording medium to a printing section and obtaining good print quality similar to that obtainable in the case of a thick recording medium. The printer comprises a first supply path for supplying a first recording medium, a second supply path for supplying a second recording medium thicker than the first recording medium, a printing section for printing on a recording medium supplied from the first supply path or the second supply path, and a delivery section for delivering the recording medium printed in the printing section. A guide spring member which is movable up and down is projected upstream of the printing section and in a meeting portion of the first supply path and the second supply path. This guide spring member serves to support a top surface of the first recording medium at a predetermined height.Type: GrantFiled: August 31, 1999Date of Patent: March 26, 2002Assignee: Seiko Precision, Inc.Inventors: Naoki Tanabe, Satoru Tada
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Patent number: 6351149Abstract: There is disclosed a MOS transistor output circuit capable of suppressing ringing and other noises and of operating at high speed under low power supply voltages. A signal corresponding to an input signal is applied to the gates of a first p-channel MOS transistor and a first n-channel MOS transistor. A control circuit detects the falling edge of the input signal to create a first signal. A second p-channel MOS transistor is held in conduction by the first signal during a period beginning with the rising edge of the output signal and ending with the instant at which the output signal can be regarded as having logic high (H) level. The rising edge of the input signal is detected to create a second signal. A second n-channel MOS transistor is held in conduction by the second signal during a period beginning with the falling edge of the output signal and ending with the instant at which the output signal can be regarded as having logic low (L) level.Type: GrantFiled: December 3, 1999Date of Patent: February 26, 2002Assignee: Nippon Precision Circuits, Inc.Inventor: Satoru Miyabe
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Patent number: 6331724Abstract: A semiconductor memory cell device exhibiting superior cell reliability comprising a dual layer floating gate wherein the thin upper layer of the floating gate overlaps the edges of surrounding field insulating regions and has rounded edges to minimize leakage concerns. The tunnel dielectric separating the dual layer floating gate from the substrate comprises a layer of uniform thickness which is grown prior to the formation of the field insulating regions. The Fowler-Nordheim tunneling mechanism is used for programming and erasing the inventive cells in a programming process flow which comprises flash programming all cells on a word line, sensing current on a selected cell, and selectively erasing the charge on the cell by applying a higher voltage on the intersecting bit line than is applied to the word line, until the sensed current is as desired.Type: GrantFiled: December 23, 1997Date of Patent: December 18, 2001Assignee: Nippon Precision Circuits, Inc.Inventors: James T. Chen, Atsuo Yagi
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Patent number: 6329884Abstract: There is disclosed an oscillator circuit in which the first capacitor is connected between the input side of a CMOS inverter in a quartz oscillator circuit and a higher potential side, the second load capacitor is connected between the input side of the inverter and a lower potential side, the third load capacitor is connected between the output side of the inverter and the higher potential side, and the fourth load capacitor is connected between the output side of the inveter and the lower potential side, so that variation in amplitudes of the voltage sources synchronized with the oscillation can be reduced with the realization of lower current consumption.Type: GrantFiled: October 8, 1998Date of Patent: December 11, 2001Assignee: Nippon Precision Circuits, Inc.Inventors: Kunihiko Tsukagoshi, Satoru Miyabe, Kazuhisa Oyama
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Patent number: 6317582Abstract: A multimode mobile telephone apparatus incorporating a transmitter; a receiver; a display unit; a dial input portion; and wireless communication means for a plurality of communication methods to establish communication with a base station, wherein the multimode mobile telephone apparatus is sectioned into single-mode portable terminals 2a and 2b with which communication is established with the base station for each communication method, a transmitter, a receiver, a display unit and a dial input portion of each of the single-mode portable terminals 2a and 2b are integrated into one shared MMI portable terminal 1, and local wireless communication means 43a, 43b, 21 is provided which establishes communication between the single-mode portable terminals 2a or 2b and the MMI portable terminal 1 by a wireless method, and selection and connection with an arbitrary single-mode portable terminals 2a or 2b are performed from the MMI portable terminal 1 through the local wireless communication means 21.Type: GrantFiled: May 4, 2000Date of Patent: November 13, 2001Assignee: Kyocera CorporationInventor: Shigehiro Yoshinaga
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Patent number: 6307537Abstract: Multifunction key switch in which a multifunction key 6 is fitted into a hole 4 formed in a front case 3 so as to be able to pivotally move in a thicknesswise direction of the front case 3, as well as to enter a plurality of different operation instructions. A hole 8 is formed so as to penetrate through the multifunction key actuation section 6 in the thicknesswise direction of the front case 3. An execution key actuation section 7 is fitted into the hole 8 and determines the operation instruction entered by way of the multifunction key actuation section 6 when being pressed in the thicknesswise direction of the front case 3.Type: GrantFiled: July 22, 1999Date of Patent: October 23, 2001Assignee: Kyocera CorporationInventor: Yasuhiko Oowada